3D Stacked Inductor-Capacitor Apparatus for Compact RF Integration
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Solution Overview
Problem
Conventional inductors and capacitors occupy excessive space and are often distant from the die in integrated circuits, making them unsuitable for compact devices like mobile computing and wearable technology, and require additional space for routing and solder balls when embedded in PCBs.
Innovation Solution
A substrate-integrated inductor-capacitor apparatus comprising stacked metal layers with spiral inductors and capacitors, where vias and pads are used to couple the layers, and a dielectric layer surrounds the apparatus, allowing for compact integration and reduced self-resonance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional inductors and capacitors are used in packaged systems, then the circuit functionality is achieved, but the surface area of the packaged system becomes too large
Solution Approach 1:
The patent combines multiple discrete components (inductors, capacitors, and interconnects) into a single integrated substrate structure. The substrate includes first and second interconnects with spiral configurations that provide both inductive and capacitive functions, eliminating the need for separate discrete components and reducing overall surface area.
Solution Approach 2:
The patent transitions from planar two-dimensional layouts to three-dimensional stacked configurations. Multiple metal layers are stacked vertically with vias providing inter-layer connections, allowing components to be positioned in three dimensions rather than requiring extensive two-dimensional routing space.
2Area of stationary object
If inductors and capacitors are placed close to the die, then the packaged system size is reduced, but the routing complexity increases
Solution Approach 1:
The substrate is segmented into multiple functional layers, with each metal layer containing specific interconnect patterns. The first interconnect includes a first spiral portion and second spiral portion, while the second interconnect includes corresponding spiral portions, allowing complex routing functions to be distributed across separate layers rather than concentrated in a single plane.
Solution Approach 2:
The patent employs nested spiral configurations where interconnects are arranged in concentric or overlapping spiral patterns. This nesting allows multiple signal paths and routing functions to be packed into compact areas, reducing the overall footprint while maintaining routing functionality.
3Area of stationary object
If inductors are embedded inside the PCB, then the surface area is reduced, but additional space is required for routing the inductor to other devices
Solution Approach 1:
The patent embeds inductors and capacitors within the substrate using vertical stacking of metal layers connected by vias. This three-dimensional integration allows components to be positioned close to the die without requiring long horizontal routing paths across the PCB surface.
4Area of stationary object
If inductors are mounted on the backside of the PCB, then the front surface area is reduced, but solder balls must be depopulated to make space
Solution Approach 1:
The patent integrates inductors, capacitors, and interconnects into a single substrate assembly that can be mounted as one unit. This eliminates the need for separate component mounting operations and associated solder ball depopulation, as the integrated substrate provides all necessary connections through its internal interconnect structure.
Data Source
AI summary
Some aspects pertain to an apparatus that includes a plurality of stacked metal layers configured in a spiral shape. The plurality of stacked metal layers include a first metal layer including a first inductor, a second metal layer including a plurality of first pads and a plurality of second pads, a third metal layer including a plurality of third pads and a plurality of fourth pads, a fourth metal layer including a second inductor, a plurality of first vias configured to couple the first metal layer to the second metal layer, a plurality of second vias configured to couple the second metal layer to the third metal layer, a plurality of third vias configured to couple the third metal layer to the fourth metal layer; and a dielectric layer at least partially surrounding the apparatus.