Stacked Inductor Chip Layout for Compact Digital Isolation
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Solution Overview
Problem
Existing semiconductor devices with digital isolators face challenges in further miniaturization due to the protrusion of one semiconductor chip from another, complicating alignment and limiting size reduction, and are prone to noise interference and electrical short circuits between high and low voltage regions.
Innovation Solution
The semiconductor device employs a design where the second semiconductor chip is joined to the first without protruding, using flip-chip connection with solder bumps for alignment, and incorporates an isolation insulating film and N-type well to block noise, along with recessed portions in the multilayer wiring structure to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one semiconductor chip protrudes from another in the digital isolator structure, then the inductors can face each other for electromagnetic induction, but the device size cannot be further reduced and alignment becomes complicated
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement to a three-dimensional stacked arrangement where the first and second semiconductor chips are positioned on top of each other. The inductors are arranged vertically with the first inductor on the first chip and the second inductor on the second chip, enabling electromagnetic induction in the vertical dimension rather than horizontal, thus reducing device footprint while maintaining signal transmission capability
Solution Approach 2:
The patent embeds the second semiconductor chip within the footprint of the first semiconductor chip by positioning it on top of the first chip. The second chip is recessed relative to the first chip, creating a nested configuration where the second chip does not protrude beyond the boundaries of the first chip, thereby minimizing the overall device volume
2Reliability
If semiconductor chips are joined with protrusion, then inductor alignment is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates alignment marks on both the first and second semiconductor chips before the joining process. These pre-formed alignment marks enable automated alignment systems to accurately position the second chip relative to the first chip during the stacking process, simplifying the manufacturing procedure and reducing alignment complexity
Solution Approach 2:
The patent replaces complex mechanical alignment procedures with automated optical or electromagnetic alignment systems that use the pre-formed alignment marks. This substitution reduces manual intervention and simplifies the manufacturing process by using non-contact or minimal-contact alignment methods
3Volume of moving object
If high voltage and low voltage regions are in close proximity, then device miniaturization is achieved, but noise interference and electrical short circuits occur
Solution Approach 1:
The patent introduces an isolation insulating film as an intermediary layer between the high voltage region and the low voltage region. This insulating film acts as a barrier that prevents direct electrical contact and reduces electromagnetic coupling between the two voltage regions, thereby suppressing noise interference and preventing electrical short circuits while allowing the regions to remain in close proximity for miniaturization
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the semiconductor device. The isolation insulating film is specifically placed at the interface between high and low voltage regions, providing localized electrical isolation and noise suppression where needed, while other regions maintain their original properties for optimal performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a 20% reduction in size, improved signal communication quality, and effective noise suppression, simplifying the manufacturing process and reducing production costs while enhancing voltage withstand capabilities.
Implementation Method 1
an electric signal is transmitted by using the electromagnetic induction between an inductor (one inductor) electrically connected to the circuit including the power semiconductor element and an inductor (the other inductor) electrically connected to the circuit including the microcomputer
Data Source
AI summary
A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed. The second semiconductor chip is joined to the first semiconductor chip such that the first coil (second coil) and the third coil (fourth coil) are overlapped and the second semiconductor chip does not have an offset structure with respect to the first semiconductor chip. The second semiconductor chip is joined to the first semiconductor chip such that it is not overlapped with a pad for the first semiconductor chip and a pad for the second semiconductor chip.