Stacked Synthetic Inductor Layout for Compact Equalization Circuits
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Solution Overview
Problem
The miniaturization of reception devices is hindered by the large occupied area of inductors used in equalization circuits, which are necessary for high-speed data transmission with low power consumption in semiconductor integrated circuits.
Innovation Solution
A semiconductor integrated circuit design that includes a synthetic inductor element with multiple inductor portions across different wiring layers, allowing for reduced occupied area while maintaining high Q values and signal amplification capabilities, achieved through a specific configuration of inductor elements and resistance elements in the equalization circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional inductor is used in the equalization circuit, then the required inductance and Q value are achieved, but the occupied area on the chip becomes large
Solution Approach 1:
The patent transitions from planar inductor布局 to a three-dimensional stacked configuration. Multiple inductor portions are arranged in different wiring layers (first wiring layer, second wiring layer) and connected via vias, effectively utilizing the vertical dimension to reduce the horizontal occupied area while maintaining the required inductance value and Q value for signal amplification
Solution Approach 2:
The inductor is divided into multiple discrete inductor portions (first inductor portion, second inductor portion, third inductor portion) distributed across different wiring layers. Each portion contributes to the total inductance, and the segmented structure allows for optimized placement and connection through vias, reducing the overall occupied area compared to a single large planar inductor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the occupied area of the inductor, lowering chip costs, facilitating placement, and minimizing interference, while maintaining high inductance and Q values, thus enabling efficient high-frequency signal amplification.
Implementation Method 1
an inductor element (10) comprising: a first inductor portion (11) provided in a first region (AR1) of a first wiring layer (WL1)... a second inductor portion (12) provided in a second region (AR2) of the first wiring layer (WL1)... a third inductor portion (13) provided at a second wiring layer (WL2)
Data Source
AI summary
A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the third inductor portion is electrically connected to a second end portion of the second inductor portion.