Triple-Stacked Integrated Inductor for Low-Resistance IC Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated inductors face challenges in achieving low resistance and high performance at a reasonable cost, often requiring complex and costly manufacturing processes, and suffer from high wire resistance and substrate losses due to via connections and line-to-line coupling capacitance.
Innovation Solution
The integration of a thick-wire inductor formed by a triple stack of metal layers, including a lower copper layer, a middle copper layer, and an upper aluminum layer, which are formed concurrently with existing IC device fabrication processes, reducing resistance and improving the quality factor Q without additional steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional thick wire inductors are formed using dedicated extra thick metal layers or multiple aluminum metal layers, then resistance is reduced and quality factor Q is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent merges the inductor wire formation with the existing IC interconnect structure by utilizing the top copper interconnect layer and aluminum bond pad layer that are already present in standard IC fabrication processes. The middle copper layer is formed concurrently with other copper vias using the same electrochemical plating process, eliminating the need for separate thick wire inductor manufacturing steps and reducing overall device complexity while maintaining low resistance.
2Ease of manufacture
If multi-layer inductors are formed with different metal layers connected through via connections using standard processes, then manufacturing cost is reduced, but wire resistance increases and quality factor Q deteriorates
Solution Approach 1:
The patent transitions from planar multi-layer inductor structures to a vertical stacked configuration where the top copper interconnect layer, middle copper layer, and aluminum bond pad layer are stacked vertically to form a thick wire. This vertical stacking in the third dimension creates an effective thick wire with low resistance while using standard process layers, achieving both low manufacturing cost and low wire resistance.
3Ease of manufacture
If inductors are formed close to the package substrate with via connections, then manufacturing is simplified, but substrate loss increases and performance deteriorates
Solution Approach 1:
The patent extracts the inductor structure from the traditional substrate-proximity configuration and repositions it to utilize the top copper interconnect layer and aluminum bond pad layer that are located farther from the package substrate. This extraction removes the inductor from the high-substrate-loss region while maintaining manufacturing simplicity by using existing standard process layers.
4Ease of manufacture
If conventional processes are used for forming integrated inductors, then manufacturing is straightforward, but line-to-line coupling capacitance increases and self-resonant frequency decreases
Solution Approach 1:
The patent segments the inductor wire into multiple distinct metal layers (top copper interconnect layer, middle copper layer, aluminum bond pad layer) that are stacked vertically. This segmentation in the vertical dimension reduces line-to-line coupling capacitance between adjacent wire segments while maintaining manufacturing straightforwardness by using standard process layers with appropriate spacing and insulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The triple-stacked inductor design achieves resistance levels below 5 mΩ/sq, enhancing the quality factor Q and reducing manufacturing costs by leveraging copper electrochemical plating to form the middle copper layer concurrently with other IC components, thus overcoming the limitations of conventional methods.
Implementation Method 1
leveraging copper electrochemical plating to form the middle copper layer
Data Source
AI summary
A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.