3D Stacked Inductor Substrate for Compact RF Front-End Packaging
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Solution Overview
Problem
The integration and miniaturization of RF front-end chips are hindered by the size and performance impact of inductors embedded in the substrate, necessitating a solution that provides a semiconductor device with large inductance values while maintaining a compact form factor and reducing production costs.
Innovation Solution
A substrate device comprising alternately stacked first insulating and functional layers with embedded inductance coils, allowing flexible positioning on a substrate without increasing its thickness or area, and incorporating features like connection holes and solder balls for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inductors are embedded into the substrate to achieve large inductance values, then the inductance performance is improved, but the thickness or area of the substrate increases
Solution Approach 1:
The patent transitions from planar inductor layouts to three-dimensional stacked functional layers. Multiple functional layers are stacked vertically with alternating insulating and conductive layers, enabling large inductance values to be achieved within a compact vertical footprint rather than expanding substrate area horizontally.
Solution Approach 2:
The patent implements nested inductance coils within the stacked functional layers, where inner coils are positioned within the projection area of outer coils in adjacent layers. This nesting arrangement maximizes the use of vertical space and achieves high inductance values without proportionally increasing the substrate area.
2Reliability
If inductors are embedded into the substrate to achieve large inductance values, then the inductance performance is improved, but the substrate area increases
Solution Approach 1:
The patent transitions from planar inductor layouts to three-dimensional stacked functional layers. Multiple functional layers are stacked vertically with alternating insulating and conductive layers, enabling large inductance values to be achieved within a compact vertical footprint rather than expanding substrate area horizontally.
Solution Approach 2:
The patent implements nested inductance coils within the stacked functional layers, where inner coils are positioned within the projection area of outer coils in adjacent layers. This nesting arrangement maximizes the use of vertical space and achieves high inductance values without proportionally increasing the substrate area.
3Ease of manufacture
If traditional substrate processes are used for manufacturing, then the manufacturing process is simple, but the integration and miniaturization of RF front-end chips is hindered
Solution Approach 1:
The patent divides the substrate into multiple discrete functional layers, each performing specific functions (inductance, capacitance, grounding, etc.). This segmentation enables independent optimization of each layer while maintaining overall system performance, and allows for modular manufacturing and assembly processes that support miniaturization.
Solution Approach 2:
The patent employs composite structures combining alternating insulating materials and conductive materials in the stacked functional layers. This composite approach enables simultaneous achievement of electrical isolation, magnetic flux confinement, and low-inductance grounding paths, supporting both manufacturing feasibility and advanced RF performance for miniaturized devices.
Data Source
AI summary
The embodiments of the present disclosure provide a substrate device and a semiconductor package, the substrate device includes: first insulating layers and first functional layers stacked alternately, each of the first functional layers having a metal pattern, where the metal pattern includes an inductance coil, and the substrate device is adaptable for being positioned on a substrate.