3D Stacked Inductor Structure for Compact Semiconductor Devices
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Solution Overview
Problem
Conventional inductors with solenoid designs have high quality factors but occupy large areas, increasing manufacturing costs and limiting their suitability for mobile and embedded applications.
Innovation Solution
The inductor structure features multiple sets of traces across different layers with tapered configurations, reducing capacitance and footprint while improving the quality factor, achieved through specific layering and connector configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional solenoid design is used, then the quality factor is improved, but the area occupied increases
Solution Approach 1:
The patent transitions from a planar inductor design to a three-dimensional stacked configuration with multiple layers of traces separated by dielectric layers. This vertical stacking allows multiple inductive paths to occupy the same footprint area, effectively increasing the quality factor without proportionally increasing the planar area occupied by the device.
Solution Approach 2:
The patent implements nested inductive structures where traces in different layers are positioned to overlap or align vertically, creating a nested configuration. The first layer traces, second layer traces, and third layer traces are arranged such that they occupy overlapping horizontal spaces, maximizing the use of available area while maintaining high quality factor through multiple contributing inductive paths.
2Area of stationary object
If the inductor area is reduced, then manufacturing cost decreases, but the quality factor may deteriorate
Solution Approach 1:
By stacking multiple layers vertically, the patent achieves high quality factor in a compact footprint. The multi-layer structure allows the inductor to maintain excellent electrical performance while occupying minimal planar area, making it suitable for mobile and embedded applications where space is constrained.
Solution Approach 2:
The patent employs composite structures combining conductive trace layers with dielectric materials between layers. This composite approach enables the creation of a compact multi-layer inductor that achieves high quality factor through the synergistic arrangement of different materials and layers, rather than relying on a single large planar structure.
3Reliability
If multiple layers with tapered traces are used, then inductance and quality factor improve, but device complexity increases
Solution Approach 1:
The patent divides the inductor structure into multiple discrete layers, each containing traces with specific configurations. The first layer, second layer, and third layer are segmented structures that can be independently designed and optimized. This segmentation allows for tapered trace configurations within each layer to maximize inductance while managing overall device complexity through modular layer design.
Data Source
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AI summary
An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.