Stacked Inductor Structure for IC Driver Circuit Transient Optimization
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Solution Overview
Problem
Conventional driver circuits in integrated circuits face challenges in optimizing transient characteristics such as rise and fall time, overshoot, and settling time, due to complex design parameters involving inductances, mutual coupling, and parasitic capacitance, which complicates the design and layout optimization of inductor configurations.
Innovation Solution
The implementation of a stacked inductor structure in an integrated circuit, comprising loops in multiple metal layers connected by vias, simplifies the design by reducing the number of design parameters and footprint, and improves performance by forming a single coil between terminals, thereby enhancing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a three terminal transformer configuration is used, then return loss is optimized, but design complexity increases due to multiple parameters
Solution Approach 1:
The patent divides the inductor into multiple separate loops distributed across different metal layers. Each loop is a distinct conductive structure that can be independently designed and optimized, reducing the interdependence of design parameters while maintaining overall performance
Solution Approach 2:
The patent transitions from a planar single-layer inductor design to a three-dimensional multi-layer stacked configuration. By distributing loops across multiple metal layers and connecting them vertically, the design achieves better return loss characteristics without the complexity of tuning multiple coupled parameters in a single plane
2Ease of operation
If conventional inductor design is used, then layout is simpler, but transient characteristics are not optimized
Solution Approach 1:
The patent employs a multi-layer stacked inductor configuration where loops are distributed across different metal layers and connected via vias. This three-dimensional arrangement optimizes transient characteristics such as rise time, fall time, and settling time without significantly complicating the layout process, as each layer can be independently patterned and connected
3Device complexity
If stacked inductor structure is implemented, then design complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the inductor into multiple loops across different metal layers, each with standardized dimensions and patterns. This segmentation allows for modular manufacturing where via alignment can be achieved through repeated reference to common alignment marks and standardized via hole positions, reducing the cumulative precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the complexity of inductor design and layout optimization, improving rise/fall time from 38 ps to 25 ps, enabling the driver to operate at higher speeds up to 25-30 Gbt/s with improved signal transmission.
Implementation Method 1
a stacked inductor structure in an integrated circuit, comprising loops in multiple metal layers connected by vias, simplifies the design by reducing the number of design parameters and footprint, and improves performance by forming a single coil between terminals
Data Source
AI summary
An inductor implemented in an integrated circuit is described. The inductor comprises a plurality of loops of the inductor in at least a first metal layer and a second metal layer of a plurality of metal layers; and a plurality of vias connecting ends of loops of the plurality of loops in different metal layers; wherein each loop of the first metal layer which is connected to a corresponding loop of the second metal layer overlies the corresponding loop of the second metal layer. A method of implementing an inductor in an integrated circuit is also described.