Stacked Insulating Layers for Semiconductor Integration Density
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to achieve higher integration density without the need for expensive equipment and complex processes, which is limited by the feature size achievable with current micropattern forming technologies.
Innovation Solution
The method involves alternatingly and repeatedly stacking sacrificial and insulating layers on a substrate, forming openings, and creating spacers on the sidewalls, followed by etching to expose the bottom surface, allowing for the formation of semiconductor layers and subsequent patterning to create trench structures and information storage layers, enabling the fabrication of semiconductor devices with improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is decreased to increase integration density, then integration degree is improved, but manufacturing cost and process complexity increase due to expensive equipment requirements
Solution Approach 1:
The patent transitions from planar (2D) device arrangement to vertical (3D) stacking of sacrificial and insulating layers. By forming openings through multiple stacked layers and creating semiconductor structures within these openings, the method achieves higher integration density in the vertical dimension without requiring proportional reduction in lateral feature size, thereby avoiding the need for extremely expensive advanced lithography equipment.
Solution Approach 2:
The patent employs a nested structure where sacrificial layers and insulating layers are alternately stacked, with openings formed through these nested layers. Semiconductor layers are then formed within these openings, creating a nested configuration that increases integration density without proportionally decreasing the lateral dimensions of individual components.
2Productivity
If feature size is decreased to increase integration density, then integration degree is improved, but device reliability deteriorates due to difficulties in achieving fine patterns
Solution Approach 1:
The patent performs preliminary actions by first forming the stacked sacrificial and insulating layers, then creating openings through these layers before forming the semiconductor structures. The spacer is formed on the sidewalls of openings in advance, and selective etching is performed to expose specific regions. This sequence of preliminary actions ensures proper alignment and structural integrity, thereby maintaining device reliability while achieving high integration density.
Solution Approach 2:
The patent introduces spacers as intermediary structures formed on the sidewalls of openings. These spacers serve as mediators that define the boundaries and positions of semiconductor layers, ensuring precise placement and structural stability. The spacer acts as an intermediate element that facilitates the formation of reliable fine patterns without directly requiring extreme lithographic resolution.
3Ease of manufacture
If conventional micropattern forming techniques are used, then manufacturing process is simple, but integration density is limited by achievable feature size
Solution Approach 1:
The patent resolves this contradiction by moving from 2D planar patterning to 3D vertical stacking. Multiple sacrificial and insulating layers are alternately deposited to form a stacked structure, with openings formed through these layers. This vertical arrangement enables higher integration density while using relatively conventional thin-film deposition and etching techniques, maintaining process simplicity while dramatically increasing the number of devices per unit area.
Solution Approach 2:
The patent segments the device structure into multiple alternating sacrificial layers and insulating layers. This segmentation allows each layer to be formed using standard thin-film deposition techniques, and the stacked configuration enables high integration density without requiring single-step complex patterning processes. The segmented structure simplifies manufacturing while achieving superior integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the stable formation of semiconductor devices with enhanced integration density, reliability, and reduced voids or seams, leading to improved performance and cost-effectiveness in semiconductor device manufacturing.
Implementation Method 1
The forming of the spacer may include conformally forming a spacer precursor layer on the substrate having the opening, and anisotropically etching the spacer precursor layer
Implementation Method 2
etching the spacer to expose the bottom surface of the opening beneath the spacer
Implementation Method 3
removing the sacrificial patterns exposed to the trench to form recess regions
Implementation Method 4
crystallizing the spacer and the semiconductor layer
Implementation Method 5
supplying heat to the spacer and the semiconductor layer
Data Source
AI summary
Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.