Stacked III-N and TFT Integration for Logic Performance
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Solution Overview
Problem
The challenge in implementing III-N transistors in high voltage and high frequency applications is the lack of viable low-voltage P-type metal-oxide-semiconductor (PMOS) transistors, limiting the use to N-type metal-oxide-semiconductor (NMOS) transistors only, which complicates logic performance and requires separate chips for PMOS and NMOS transistors, increasing the number of input/output pins and compromising the solution's viability.
Innovation Solution
Integrating thin-film transistors (TFTs) monolithically with III-N transistors on the same support structure, allowing for the stacked integration of PMOS transistors alongside NMOS transistors, thereby enabling compact implementation and reducing the need for separate chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate chips are used for PMOS and NMOS transistors, then device functionality is achieved, but the number of input/output pins increases and device complexity increases
Solution Approach 1:
The patent combines PMOS and NMOS transistors into a single integrated chip by stacking them vertically. The PMOS transistor is positioned above the NMOS transistor, sharing common source and drain regions, which eliminates the need for separate chips and reduces the number of input/output pins required.
Solution Approach 2:
The patent transitions from a planar arrangement to a vertical three-dimensional structure by stacking the PMOS and NMOS transistors one above the other. This vertical integration allows both transistor types to coexist on the same chip footprint, reducing the overall device complexity and pin count.
2Reliability
If III-N transistors are used for high voltage and high frequency applications, then performance is improved, but the lack of P-type transistors limits logic performance
Solution Approach 1:
The patent merges III-N material transistors with oxide semiconductor transistors in a stacked configuration. The III-N transistor provides high voltage and high frequency performance, while the oxide semiconductor transistor enables P-type functionality, together achieving both high reliability and improved logic performance.
Solution Approach 2:
The patent employs a composite structure combining III-N materials (gallium nitride, aluminum gallium nitride) with oxide semiconductor materials. This composite approach leverages the high electron mobility and breakdown voltage of III-N materials while utilizing the P-type capability of oxide semiconductors to achieve full CMOS logic functionality.
3Area of stationary object
If stacked integration is implemented, then total surface area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes vertical stacking to reduce the horizontal footprint of the device. By arranging PMOS and NMOS transistors in the vertical dimension rather than placing them side-by-side in the plane, the total surface area is significantly reduced while maintaining full functionality.
Solution Approach 2:
The patent divides the transistor structure into distinct stacked segments with clear functional separation. The PMOS transistor stack and NMOS transistor stack are segmented into different vertical levels, with shared source/drain regions at the bottom and separate gate structures above, simplifying the manufacturing process despite the three-dimensional arrangement.
Data Source
AI summary
Disclosed herein are integrated circuit (IC) structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. One example IC structure includes an III-N transistor in a first layer over a support structure (e.g., a substrate) and a TFT in a second layer over the support structure, where the first layer is between the support structure and the second layer. Another example IC structure includes a III-N semiconductor material and a TFT, where at least a portion of a channel material of the TFT is over at least a portion of the III-N semiconductor material.