Stacked Semiconductor Interconnects Using Self-Aligned Blind Holes
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Solution Overview
Problem
Current semiconductor interconnect fabrication methods, such as Through Silicon Vias (TSVs) and die-to-die or die-to-wafer bonding, face inefficiencies and high costs due to alignment errors, connection defects, and low yield, particularly in forming electrical connections between stacked chips.
Innovation Solution
A method involving the formation of blind holes in stacked semiconductor structures, where a first blind hole is created between metal wires and expanded to expose wire ends, allowing for the filling of conductive material to form TSVs without the need for bumps, thereby simplifying the interconnect process and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-to-die or die-to-wafer bonding with bumps and TSVs is used, then electrical connections between stacked chips are established, but the manufacturing process becomes complicated and yield decreases due to alignment errors and connection defects
Solution Approach 1:
The patent merges the TSV formation and bump formation processes into a single integrated process. The blind holes are formed to expose metal wire end surfaces, and conductive material is filled to create both the via and bump structures simultaneously, eliminating the need for separate bump formation and reducing alignment requirements between layers
Solution Approach 2:
The patent performs preliminary actions by forming the blind holes and exposing metal wire end surfaces before final bonding. The conductive material is pre-filled in the blind holes to create ready-to-connect structures, so that when layers are bonded, the electrical connections are already prepared and aligned by the etching process itself rather than requiring post-bonding bump formation
2Reliability
If TSVs and bumps are formed for each chip before bonding, then electrical connections are established, but alignment and connection errors increase, resulting in low yield
Solution Approach 1:
The patent combines TSV formation and bump formation into one process where the same blind hole etching defines both the via location and the bump location. The metal wire end surfaces exposed by the etching serve as both the via anchor and the bump formation site, eliminating alignment errors between separate TSV and bump processes
Solution Approach 2:
The etching process itself performs the alignment function by automatically exposing the metal wire end surfaces at the correct positions. The process self-aligns the conductive material filling to the metal wires, and the subsequent bonding interfaces are self-aligned by the exposed wire ends, eliminating the need for external alignment mechanisms
3Productivity
If traditional bump-based bonding is used, then electrical connections are established, but the process requires multiple steps including TSV formation, bump formation, and bonding, reducing productivity
Solution Approach 1:
The patent merges multiple process steps into fewer operations: blind hole etching that exposes metal wires, conductive material filling that creates both via and bump structures, and direct bonding. This reduces the total number of process steps from traditional multi-step TSV-bump-bonding sequences to an integrated process flow
Solution Approach 2:
The patent performs preliminary formation of the conductive structures before bonding, so that when layers are stacked and bonded, the electrical connections are already in place. This eliminates post-bonding processing steps and accelerates the overall manufacturing cycle
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the interconnect process, reduces manufacturing costs, and enhances the yield of semiconductor interconnects by directly bonding layers and forming TSVs through a single etching process, avoiding alignment issues and connection defects associated with traditional bump-based methods.
Implementation Method 1
a seed metal is sputtered on the exposed end surfaces of the plurality of metal wires and an inner surface of the blind hole
Data Source
AI summary
A semiconductor interconnect structure and a fabricating method thereof are disclosed. The method comprises: providing a stacked structure comprising bonded multiple layers of wafer or die, each bonded layer comprises a substrate and a wiring layer, and the wiring layer comprises metal wires; vertically forming, in the stacked structure, a first blind hole having a first diameter and a first length and penetrating each bonded layer between adjacent metal wires, the first diameter is less than a space between the adjacent metal wires, and the first length is less than a height of the stacked structure; forming a second blind hole having a second diameter and the first length coaxially with the first blind hole, a sidewall of the second blind hole exposes the metal wires, and the second diameter is larger than the space between the adjacent metal wires; and filling a conductive material in the second blind hole.