Stacked Interconnect Inductor for Low Resistance Logic Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Inductors formed by standard logic processes have high resistance and poor Q factors due to thinner metal layers, whereas those formed by RF processes are costly and thick, leading to high fabrication costs.
Innovation Solution
A semiconductor device with a top level interconnect metal layer, a below-to-top level interconnect metal layer, and a via plug pattern, all with parallel profiles, electrically connected to reduce resistance and improve Q factors without using additional metal layers or costly RF processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a very thick metal layer is used to form inductors in RF process, then resistance is reduced and Q factor is improved, but fabrication cost increases
Solution Approach 1:
The patent transitions from a single-layer thick metal structure to a multi-layer stacked structure with via plugs connecting multiple thinner metal layers. This dimensional change allows achieving equivalent or superior electrical performance through vertical stacking rather than relying on a single thick layer, thereby reducing fabrication costs while maintaining Q factor.
Solution Approach 2:
The inductor is constructed as a composite structure combining multiple metal layers separated by dielectric materials, connected through via plugs. This composite approach allows optimization of each layer's thickness and material properties, achieving low resistance and high Q factor without requiring a single expensive thick metal layer.
2Ease of manufacture
If standard logic process is used to form inductors, then fabrication cost is reduced, but resistance increases and Q factor deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple standard logic process metal layers with via plugs to create a thick effective conductor. This allows achieving low resistance and high Q factor characteristics typically requiring thick RF metal layers, but using only standard logic process thinner layers, thereby maintaining low fabrication cost.
Solution Approach 2:
The inductor structure segments the current path into multiple parallel metal layers connected by via plugs. This segmentation allows each layer to contribute to current conduction, effectively reducing total resistance while using only standard logic process thickness layers, thus achieving high Q factor at low fabrication cost.
3Reliability
If multiple metal layers are stacked with parallel profiles, then resistance is reduced and Q factor is improved, but device structure becomes more complex
Solution Approach 1:
The patent uses standard interconnect metal layers and via plugs, which are universal components already present in semiconductor interconnect structures. By utilizing these existing universal elements for inductor formation, the patent reduces structure complexity compared to designing entirely new components, while still achieving low resistance and high Q factor.
Data Source
AI summary
A semiconductor device and an inductor are provided. The semiconductor device includes a top level interconnect metal layer (Mtop) pattern. A below-to-top level interconnect metal layer (Mtop−1) pattern is disposed directly below the top level interconnect metal layer pattern. A first via plug pattern is vertically disposed between the top level interconnect metal layer pattern and the below-to-top level interconnect metal layer pattern, electrically connected to the top level interconnect metal layer pattern and the below-to-top level interconnect metal layer pattern. The top level interconnect metal layer pattern, the below-to-top level interconnect metal layer pattern and the first via plug pattern have profiles parallel with each other from a top view.