Stacked Interconnect Structure Warpage Control

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Solution Overview

Problem

Miniaturized interconnect structures in electronic equipment face challenges such as warpage, poor electrical connections, and void formation due to thin substrates, leading to increased complexity and yield loss in manufacturing.

Innovation Solution

An interconnect structure is designed with a stacked configuration of substrates and polymeric layers, where the first substrate has a cavity and recesses, and the second substrate is thicker to prevent warpage, with polymeric layers filling the gaps to minimize voids and ensure smooth flow, thereby enhancing structural integrity and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the substrate is made thinner to miniaturize the interconnect structure, then the size is reduced, but warpage and void formation occur

Engineering Contradiction:
Improveinterconnect structure sizeVSAvoidstructural integrity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The substrate is divided into multiple stacked substrates (first substrate, second substrate, third substrate) with different thicknesses. The thinner first substrate enables miniaturization while the thicker second and third substrates provide structural support and prevent warpage, resolving the contradiction between size reduction and structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the stacked substrate structure have different thicknesses tailored to their specific functions. The first substrate layer is thinner for miniaturization in the active interconnect region, while the second and third substrate layers are thicker to provide mechanical support and prevent warpage, achieving local optimization of both size and structural integrity.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If manufacturing operations are increased to achieve greater functionality in miniaturized structures, then functionality is improved, but manufacturing complexity and yield loss increase

Engineering Contradiction:
ImprovefunctionalityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into separate operations for each substrate layer. Each substrate can be prepared, processed, and quality-checked independently before stacking, which simplifies the overall manufacturing process despite the multi-functional requirements of the miniaturized interconnect structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple substrate layers are prepared in advance with their respective features (through-holes, conductive layers, insulating layers) before the final stacking operation. This preliminary preparation allows for independent optimization and quality control of each layer, reducing manufacturing complexity and yield loss while achieving greater functionality.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If polymeric material is flowed into cavities to fill gaps, then void formation is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvevoid formationVSAvoidgap filling precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Cavities are pre-formed in the substrate layers before the polymeric material is flowed in. This preliminary cavity formation ensures that the gaps are properly positioned and sized, allowing the polymeric material to fill them effectively and reduce void formation while maintaining manageable manufacturing precision requirements.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10157839B1Interconnect structure and manufacturing method thereof
Publication Date: 2018.12.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10157839B1 patent drawing
  • US10157839B1 patent drawing
  • US10157839B1 patent drawing

AI summary

An interconnect structure includes a first substrate including a first surface, a second surface opposite to the first surface, a cavity extended through the first substrate, and a first recess extended from the second surface towards the first surface; a second substrate disposed opposite to the second surface of the first substrate; an electronic device disposed within the cavity; a first polymeric layer disposed over the first surface and within the cavity of the first substrate; and a second polymeric layer disposed between the first substrate and the second substrate and within the first recess.