Stacked Interconnection Plates for Top-Side Cooling
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Solution Overview
Problem
Existing semiconductor package designs fail to effectively achieve top-side cooling while maintaining compatibility with industry standard package pin outs, as they face a trade-off between maximizing top metal exposure for heat dissipation and ensuring adequate electrical connections, leading to limited effectiveness in thermal management.
Innovation Solution
A top-side cooled semiconductor package with stacked interconnection plates, where elevation-adaptive intimate interconnection plates are used to bond the semiconductor die to the circuit substrate, and additional stacked interconnection plates provide effective top-side cooling, with a molding encapsulant exposing the top surface of the stacked plates for heat dissipation, while maintaining structural integrity and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If top metal exposure is maximized for heat dissipation, then top-side cooling efficacy is improved, but electrical connection adequacy deteriorates
Solution Approach 1:
The interconnection structure is divided into multiple separate plates (first interconnection plate, second interconnection plate, third interconnection plate) with distinct functions. The first plate provides electrical connection, the second plate provides thermal conduction, and the third plate provides additional electrical connection. This segmentation allows each plate to be optimized for its specific function without compromising other requirements.
Solution Approach 2:
Different regions of the package are assigned different properties: the first interconnection plate region is optimized for electrical conductivity, the second interconnection plate region is optimized for thermal conductivity, and the third interconnection plate region is optimized for electrical connection. This local differentiation allows simultaneous optimization of electrical and thermal performance.
2Temperature
If stacked interconnection plates are added for top-side cooling, then thermal resistance is reduced, but device complexity increases
Solution Approach 1:
Each interconnection plate is designed to serve multiple functions simultaneously. For example, the first interconnection plate provides both electrical connection and structural support. The second interconnection plate provides thermal conduction while also serving as a mechanical spacer. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The interconnection plates are arranged in a stacked, nested configuration where the second interconnection plate is positioned atop the first, and the third interconnection plate is positioned atop the second. This nested arrangement maximizes space utilization and allows the plates to support each other structurally, reducing the need for additional support structures.
3Reliability
If intimate interconnection plates are used for electrical connection, then electrical resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The first interconnection plate is pre-formed with connection structures (such as protrusions or recesses) that align with corresponding structures on the semiconductor die and circuit substrate. This preliminary preparation of connection interfaces simplifies the bonding process and reduces manufacturing complexity by eliminating the need for complex real-time alignment mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances top-side cooling efficacy by maximizing exposed surface area for heat dissipation without compromising electrical connections, reducing thermal and electrical resistance, and ensuring compatibility with industry standard package pin outs.
Implementation Method 1
A first number of elevation-adaptive low thermal and electrical resistance intimate interconnection plates for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate
Implementation Method 2
low thermal and electrical resistance intimate interconnection plates for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate
Data Source
AI summary
A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.