Stacked Interposer Semiconductor Package for Compact SiP Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing package size and minimizing signal loss in System-in-Package (SiP) technologies, despite advancements like Double Side Molding (DSM).
Innovation Solution
A semiconductor package design featuring a substrate with interposers, where a first interposer supports electronic components, and a second interposer with a concave and protruding portion is stacked above, reducing size and enhancing connectivity through redistribution layers and heat-transfer passages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Double Side Molding (DSM) technology is used to shrink package size, then integration density is improved, but package size still increases and signal loss occurs
Solution Approach 1:
The patent implements a stacked configuration where a first interposer with first electronic components is placed on the substrate, and a second interposer with second electronic components is stacked above the first interposer. This nesting arrangement in the vertical direction enables higher integration density without increasing the horizontal package footprint, effectively resolving the contradiction between integration density and package size.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture by adding the vertical dimension. Multiple interposers and electronic components are arranged in layers along the vertical axis, allowing compact integration while maintaining small package dimensions and reducing signal loss compared to extended planar configurations.
2Adaptability or versatility
If more electronic components are integrated in a compact space, then functionality is improved, but signal loss increases
Solution Approach 1:
The patent introduces interposers as intermediary structures between the substrate and electronic components, and between stacked components. These interposers provide controlled impedance pathways and signal routing that minimize signal degradation, enabling high-functionality integration while maintaining signal integrity in the compact stacked configuration.
Solution Approach 2:
By stacking components vertically rather than spreading them horizontally, the patent reduces the signal path length through the packaging medium. The three-dimensional arrangement minimizes the distance signals must travel through lossy materials, thereby reducing signal loss while maintaining high functionality through increased component density in the vertical dimension.
Data Source
AI summary
A semiconductor package and a method for making the same are provided. The semiconductor package includes: a substrate having a lower substrate surface and an upper substrate surface; a first interposer attached on the upper substrate surface; at least one first electronic component mounted on and electronically connected with the first interposer; a second interposer disposed above the at least one first electronic component, wherein the second interposer has a concave portion and a protruding portion, the at least one first electronic component is accommodated in the concave portion, and the protruding portion is mounted on the upper substrate surface; and at least one second electronic component mounted on and electronically connected with the second interposer.