Stacked Inverter Amplifier With Current Reuse for Low-Noise Front Ends

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Solution Overview

Problem

Existing amplifiers for sensor systems face a significant challenge in balancing noise suppression and power consumption, with front-end amplifiers often dominating the system power budget and not scaling well with technology advancements, particularly in low-noise applications.

Innovation Solution

A highly power-efficient amplifier design that achieves significant current reuse by vertically stacking inverters and splitting the capacitor feedback network, allowing for reduced power consumption while maintaining low noise performance, suitable for applications with stringent power or energy requirements such as biomedical implants and IoT technologies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional front-end amplifiers are used to suppress noise below a target level, then noise performance is improved, but power consumption increases significantly

Engineering Contradiction:
Improvenoise performanceVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The amplifier is segmented into multiple inverter stages (first inverter, second inverter, third inverter) that process the signal in sequence. Each inverter stage contributes to noise suppression while sharing the power consumption burden, allowing the system to achieve low noise performance without requiring a single high-power amplifier stage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple inverter stages are merged into a unified amplifier architecture where the output of one inverter feeds into the next. This combining of multiple low-power stages achieves the cumulative noise suppression effect of a high-power amplifier while maintaining low overall power consumption

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If amplifier power is increased to dominate the system power budget for low-noise performance, then noise is suppressed, but the amplifier takes up a significant portion of the overall system power budget

Engineering Contradiction:
Improvenoise suppressionVSAvoidsystem power budget allocation
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The power consumption is segmented across multiple inverter stages rather than being concentrated in a single high-power amplifier. This segmentation allows the system to achieve noise suppression without any single component dominating the power budget, distributing the power allocation more evenly throughout the system

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The design changes the operating parameters of each inverter stage to operate in a regime where they contribute to noise suppression while consuming minimal power. By optimizing the bias conditions and transistor sizing of each inverter, the system achieves effective noise suppression without requiring excessive power from any individual stage

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11223335B2Inverter stacking amplifier
Publication Date: 2022.01.11 BOARD OF RGT THE UNIV OF TEXAS SYST
  • US11223335B2 patent drawing
  • US11223335B2 patent drawing
  • US11223335B2 patent drawing

AI summary

The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.