Stacked Integrated Passive Devices for Higher Capacitance Density
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and small footprint packaging due to limitations in current semiconductor packaging techniques, particularly in Package-on-Package (PoP) technology, where enhancing component density and functionality while minimizing device size is hindered by the need for more creative and efficient packaging methods.
Innovation Solution
The development of a semiconductor device with integrated passive devices (IPDs) involves forming a redistribution structure on a carrier substrate, adhering IPD dies with passive components, encapsulating them, and connecting them through vias to achieve a stacked configuration that increases capacitance without increasing the overall footprint, utilizing techniques like metallization patterns, dielectric layers, and encapsulants to facilitate efficient electrical connections and compact packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package (PoP) technology is used to increase integration density, then component density and functionality are enhanced, but device footprint size increases
Solution Approach 1:
The patent implements three-dimensional stacking of semiconductor dies vertically rather than arranging components horizontally. Multiple dies are stacked in the Z-direction and interconnected through through-silicon vias (TSVs), transforming the layout from two-dimensional planar arrangement to three-dimensional vertical architecture. This dimensional transition enables higher component density without proportionally increasing the device footprint area.
Solution Approach 2:
The patent embeds passive devices (capacitors, resistors, inductors) within the semiconductor dies themselves during the semiconductor fabrication process, rather than adding them as separate external components. The passive devices are integrated into the die structure at the same time as active devices, creating a nested configuration where passive components are contained within the same substrate as active components. This integration eliminates the need for additional packaging space for separate passive components.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into multiple separate dies that are stacked and interconnected. Each die can be fabricated using standard semiconductor manufacturing processes at conventional feature sizes, avoiding the need to reduce minimum feature size across the entire device. The segmentation into stackable dies with TSV interconnects allows high integration density to be achieved through vertical stacking rather than horizontal miniaturization, thereby reducing manufacturing complexity.
3Quantity of substance
If passive devices are integrated into semiconductor dies, then capacitance and functionality are enhanced without increasing footprint, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the fabrication of passive devices with the fabrication of active devices in the same semiconductor manufacturing process sequence. Passive devices such as capacitors are formed using the same deposition, patterning, and etching steps that create active device structures. The passive device electrodes and dielectric layers are integrated into the same process flow as transistor gates and interconnect layers, allowing both device types to be manufactured simultaneously in the same fabrication line without requiring separate manufacturing processes.
Data Source
AI summary
Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.