Stacked IPD Capacitors in Semiconductor Packages With Lower ESR
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes for increased integration density, challenges arise in the fabrication processes of semiconductor devices, particularly in forming high-efficiency capacitors with low equivalent series resistance (ESR) for improved performance in electronic applications.
Innovation Solution
The formation of vertically stacked integrated passive devices (IPDs), such as deep trench capacitors (DTCs), with alternating conductive and dielectric layers, and the use of interconnect structures to reduce ESR and enhance capacitance, allowing for the creation of high-efficiency capacitors within semiconductor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional problems arise in fabrication processes
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked three-dimensional structures. By stacking multiple capacitor layers in the vertical dimension, the design achieves higher integration density without further reducing minimum feature sizes in the lateral plane, thereby avoiding the fabrication process challenges associated with smaller features.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor elements are stacked within a vertical column, with each capacitor nested within the same lateral footprint. This nesting approach maximizes space utilization and increases integration density while maintaining manufacturable feature sizes.
2Reliability
If conventional capacitor structures are used, then fabrication is simpler, but equivalent series resistance (ESR) is higher and capacitance efficiency is lower
Solution Approach 1:
The patent employs vertical stacking of capacitor layers to reduce ESR and increase capacitance efficiency. By extending the capacitor structure into the vertical dimension with multiple alternating conductive and dielectric layers, the effective capacitance increases while the equivalent series resistance decreases due to shorter current paths and parallel conduction paths.
Solution Approach 2:
The patent uses composite structures with alternating conductive and dielectric materials to form the stacked capacitor. This composite approach combines materials with complementary properties to achieve both low ESR and high capacitance, with conductive layers providing charge storage and dielectric layers providing insulation and electric field confinement.
3Reliability
If vertically stacked integrated passive devices are formed, then ESR is reduced and capacitance is increased, but fabrication process complexity increases
Solution Approach 1:
The patent segments the capacitor into multiple discrete layers (conductive layers and dielectric layers) that are formed sequentially. Each layer can be independently optimized and fabricated using standard semiconductor deposition and patterning processes, making the complex structure manufacturable through modular fabrication steps.
Solution Approach 2:
The stacked IPD structure serves multiple functions simultaneously: it provides high capacitance, low ESR, and can be integrated with other semiconductor devices on the same substrate. The same fabrication process can form multiple passive devices (capacitors, resistors, inductors) using the same alternating layer structure, reducing overall process complexity.
Data Source
AI summary
An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.