Semiconductor Package Layout With Stacked IPDs for Low-ESR Decoupling
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing minimum feature sizes, leading to issues in the fabrication processes of semiconductor devices, such as increased complexity and inefficiencies in integrating high-efficiency capacitors with low equivalent series resistance (ESR) in densely packed electronic components.
Innovation Solution
The implementation of vertically stacked integrated passive devices (IPDs), including deep trench capacitors (DTCs) and metal-insulator-metal (MIM) capacitors, electrically coupled through solder connections and via connections, within a package structure that allows for high-capacitance decoupling and reduced ESR, utilizing specific materials and patterning techniques for layer formation and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but fabrication process complexity and inefficiencies increase
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked three-dimensional configurations. Multiple capacitor layers are stacked in the vertical dimension, allowing increased capacitance and integration density without proportionally increasing planar footprint or fabrication complexity. The stacked architecture enables more components to be integrated into a given area by utilizing the third dimension.
2Reliability
If vertically stacked IPDs are implemented to increase capacitance and reduce ESR, then high-efficiency decoupling is achieved, but manufacturing process complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple discrete layers (first capacitor layer, second capacitor layer, third capacitor layer) with intermediate dielectric layers between them. Each layer can be formed using separate deposition and patterning processes, allowing for modular manufacturing. This segmentation enables the complex stacked structure to be built incrementally through repeated application of standard fabrication steps, rather than requiring a single complex process.
Solution Approach 2:
The patent implements a nested structure where capacitor layers are embedded within dielectric layers, which are in turn embedded within the substrate or package structure. The first capacitor layer is formed in a first dielectric layer, the second capacitor layer in a second dielectric layer, and so on. This nesting approach allows complex multi-layer structures to be manufactured using sequential deposition and patterning of simpler individual layers.
3Quantity of substance
If deep trench capacitors and MIM capacitors are vertically stacked with solder and via connections, then capacitance values and integration density are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms conductor patterns and capacitor structures in a predetermined sequence during the fabrication process. Dielectric layers are deposited and patterned before subsequent capacitor layers are formed, establishing alignment references in advance. This preliminary formation of structural elements with defined geometries and positions enables precise alignment of subsequent layers without requiring post-fabrication adjustment.
Data Source
AI summary
An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.