Stacked IPD Package Layout for Higher Density PCB Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller, more advanced packaging systems for integrated passive device (IPD) packages with increased integration density, requiring reduced feature sizes and more efficient use of space on printed circuit boards (PCBs) while maintaining electrical performance and reducing parasitic effects.
Innovation Solution
The development of an integrated passive device (IPD) package with multiple encapsulated dies, featuring vertically stacked layers, reduced PCB area usage, customizable designs, and surface-mount technology compatibility, utilizing a carrier substrate with a release layer and redistribution layers (RDLs) for efficient die placement and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging systems are used, then manufacturing and assembly are simpler, but integration density is lower and PCB area usage is higher
Solution Approach 1:
The patent transitions from traditional planar packaging to a three-dimensional stacked architecture where multiple dies are vertically arranged and interconnected via through-silicon vias (TSVs). This vertical stacking enables higher integration density by utilizing the third dimension (height) rather than only expanding horizontally on the PCB, thereby resolving the contradiction between increased integration density and packaging complexity.
Solution Approach 2:
The patent implements a nested structure where multiple functional dies are stacked within a single package footprint, with each die containing specific passive components (inductors, capacitors, resistors) that are interconnected through vertical vias. This nesting approach allows multiple components to occupy the same spatial footprint, significantly increasing integration density while managing complexity through modular die design.
2Quantity of substance
If feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the integrated passive device into multiple separate functional dies, each dedicated to specific passive components (inductors on one die, capacitors on another, resistors on a third). This segmentation allows each die to be optimized independently for its specific function and manufactured with appropriate precision levels, then combined through standardized TSV interconnections, thereby achieving high component density without uniformly increasing manufacturing precision across all features.
3Area of stationary object
If vertically stacked layers are implemented, then component density increases and PCB area is reduced, but device complexity increases
Solution Approach 1:
The patent creates a universal stacked package architecture that can accommodate different combinations of passive components (inductors, capacitors, resistors) across multiple dies. The same basic package structure, TSV interconnection methodology, and bonding processes can be applied regardless of the specific component mix or number of dies, thereby reducing PCB area through vertical stacking while managing complexity through standardized multi-functional packaging processes.
Data Source
AI summary
An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.