Stacked Vertically Isolated MOSFET Structure for High Integration Density
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, achieving vertical isolation between channel layers, source/drain regions, and gates in MOSFETs becomes increasingly challenging, limiting the integration density and independent operation of multiple transistors on the same footprint.
Innovation Solution
The development of stacked metal-oxide-semiconductor field-effect transistors (MOSFETs) with vertical isolation, where alternating buffer and channel layers form a fin structure, and gate stacks are formed within these layers, allowing for independent MOSFET devices to be created on the same footprint, using techniques such as etching and conformal deposition of gate spacers, insulators, and metal pads, with isolation layers separating the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but vertical isolation between channel layers, source/drain regions, and gates becomes increasingly challenging
Solution Approach 1:
The patent transitions from planar transistor layouts to vertically stacked MOSFET structures, moving the integration solution into the third dimension. Multiple channel layers are stacked vertically with gate stacks positioned between them, enabling higher integration density without compromising isolation. The vertical stacking allows independent gate control of each transistor while maintaining electrical isolation through carefully engineered dielectric layers positioned between adjacent channel layers and around source/drain regions.
Solution Approach 2:
The patent divides the transistor structure into segmented, independently controllable units. Each MOSFET in the stack has its own gate stack that can be independently formed and controlled. The channel layers are separated by dielectric materials, creating electrically isolated segments. This segmentation allows each transistor to operate independently while maintaining compact vertical integration, resolving the isolation challenge at reduced feature sizes.
2Productivity
If multiple transistors are stacked vertically to improve integration density, then more devices fit on the same footprint, but achieving independent gate operation and electrical isolation becomes more difficult
Solution Approach 1:
The patent introduces dielectric materials as intermediary layers between adjacent channel layers and around source/drain regions. These dielectric intermediaries provide electrical isolation that enables independent gate operation of each stacked transistor. The gate stacks themselves act as intermediaries, positioned between channel layers to provide both control functionality and electrical separation, ensuring reliable independent operation while maintaining vertical integration.
Solution Approach 2:
The patent applies different material properties and structural configurations to different regions of the stacked structure. Dielectric materials with specific properties are placed between channel layers where isolation is needed, while conductive materials are positioned for gate control functionality. This local differentiation of material quality and structural configuration enables simultaneous achievement of electrical isolation and independent gate operation in the vertical stack.
Data Source
AI summary
A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed. In an embodiment, the method may include depositing a first buffer layer over a substrate; depositing a first channel layer over the first buffer layer; depositing a second buffer layer over the first channel layer; depositing a second channel layer over the second buffer layer; depositing a third buffer layer over the second channel layer; etching the first buffer layer, the first channel layer, the second buffer layer, the second channel layer, and the third buffer layer to form a fin structure; etching the first buffer layer, the second buffer layer, and the third buffer layer to form a first plurality of openings; forming a first gate stack in the first opening disposed in the first buffer layer, a second gate stack in the first opening disposed in the second buffer layer, and a third gate stack in the first opening disposed in the third buffer layer; and replacing the second buffer layer and a portion of the second gate stack with an isolation structure.