Stacked Layer Vertical Portion Removal for Chip Density

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Solution Overview

Problem

In the formation of integrated circuits, the interface regions between different types of devices on a chip occupy significant chip area, limiting the overall density of devices due to the presence of vertical portions of stacked layers.

Innovation Solution

The method involves forming stacked layers with horizontal portions only by etching vertical portions of conformal layers deposited in trenches, using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions and selectively remove vertical portions, thereby reducing the interface area between devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical portions of stacked layers are retained to provide structural support and device functionality, then device performance is maintained, but chip area occupied by interface regions increases, reducing overall device density

Engineering Contradiction:

Improvedevice performanceVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the vertical portions of stacked layers at interface regions while retaining horizontal portions. This selective removal eliminates unnecessary chip area occupation in interface regions while preserving the structural support and device functionality provided by the stacked layers in active device regions.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the stacked layers into different portions: horizontal portions are retained in active device regions to maintain device performance, while vertical portions are removed in interface regions to reduce chip area. This segmentation allows different parts of the stacked layers to serve different functions in different spatial locations.

Inventive Principle:

Principle #1Segmentation

2Stability of the object's composition

If interface regions are enlarged to accommodate vertical portions of stacked layers, then structural integrity is maintained, but device density decreases

Engineering Contradiction:

Improvestructural integrityVSAvoiddevice density

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating the treatment of stacked layers in different regions: in active device regions, full stacked layers (both horizontal and vertical portions) are retained to ensure structural integrity and device functionality, while in interface regions, only horizontal portions are retained to minimize chip area occupation. This localized differentiation optimizes both structural integrity and device density.

Inventive Principle:

Principle #3Local quality

3Device complexity

If conventional etching processes are used without passivation, then processing steps are simplified, but horizontal portions of stacked layers cannot be selectively preserved while removing vertical portions

Engineering Contradiction:

Improveprocessing stepsVSAvoidselective layer removal

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming passivation layers on the horizontal portions of stacked layers before performing the isotropic etching process. This preliminary passivation protects the horizontal portions from being removed during etching, enabling selective removal of only the vertical portions while preserving the horizontal portions for structural support.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The passivation layer acts as an intermediary between the stacked layers and the etching process. It selectively protects the horizontal portions of stacked layers during isotropic etching, allowing precise control over which portions are removed and which are retained, thereby achieving the desired manufacturing precision.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the chip area occupied by interface regions, increasing device density by eliminating vertical portions of stacked layers, allowing for more efficient integration of various transistor types on a single chip.

Implementation Method 1

using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions and selectively remove vertical portions

Methodology Applied

Scientific EffectAnisotropic etching:

Implementation Method 2

using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions and selectively remove vertical portions

Methodology Applied

Scientific EffectIsotropic etching:

Implementation Method 3

using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions and selectively remove vertical portions

Methodology Applied

Scientific EffectPassivation:

Data Source

PatentUS11488858B2Methods for forming stacked layers and devices formed thereof

Publication Date: 2022.11.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.