Stacked Semiconductor Layers Without Vertical Interface Portions

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Solution Overview

Problem

In the formation of integrated circuits, the interface regions between different types of devices on a chip occupy significant chip area, limiting the overall density of devices due to the presence of vertical portions of stacked layers.

Innovation Solution

The method involves forming stacked layers with horizontal portions only by etching vertical portions of conformal semiconductor layers, using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions, thereby reducing the interface area between devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical portions of stacked layers are retained to maintain structural integrity and device functionality, then device reliability is improved, but chip area occupied by interface regions increases

Engineering Contradiction:

Improvedevice reliabilityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the vertical portions of stacked layers at interface regions while retaining horizontal portions. This selective removal reduces the chip area occupied by interface regions between different device types (FinFET, nano-sheet, GAA transistors) while maintaining the structural integrity and functionality of each device type through their respective horizontal portions.

Inventive Principle:

Principle #2Taking out (Extraction)

2Productivity

If vertical portions of stacked layers are removed to reduce interface area, then device density is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvedevice densityVSAvoidmanufacturing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the stacked layers into vertical portions and horizontal portions, then selectively removes the vertical portions at interface regions. This segmentation approach enables precise control over which portions are removed, allowing increased device density while managing manufacturing complexity through a systematic process of forming, filling, and selective removal.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different treatments to different portions of the stacked layers: vertical portions at interface regions are removed to reduce area, while horizontal portions are retained to maintain device functionality. This local quality approach ensures that each portion serves its specific function, optimizing both density and reliability.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If interface regions are reduced to increase device density, then chip area efficiency is improved, but device functionality may be compromised

Engineering Contradiction:

Improvechip area efficiencyVSAvoiddevice functionality

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from a three-dimensional stacked structure with vertical portions to a predominantly two-dimensional structure with horizontal portions only at interface regions. This dimensional change reduces the vertical footprint of interface regions, improving chip area efficiency while the horizontal portions maintain the necessary device functionality through their extended structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the chip area occupied by interface regions, increasing device density by selectively removing vertical portions of stacked layers, allowing for more efficient integration of various transistor types on a single chip.

Implementation Method 1

using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions

Methodology Applied

Scientific EffectAnisotropic etching:

Implementation Method 2

using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions

Methodology Applied

Scientific EffectIsotropic etching:

Implementation Method 3

using anisotropic and isotropic etching processes with passivation layers to protect horizontal portions

Methodology Applied

Scientific EffectPassivation:

Data Source

PatentUS11942363B2Methods for forming stacked layers and devices formed thereof

Publication Date: 2024.03.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.