Stacked Semiconductor Layers to Shrink FinFET-GAA Interface Area
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Solution Overview
Problem
The challenge in integrated circuit formation is the high occupancy of chip area by interface regions between different types of devices, such as FinFET transistors and Gate-All-Around (GAA) transistors, which hinders device density improvement.
Innovation Solution
A method involving the formation of stacked layers with conformal semiconductor and passivation layers, followed by selective etching to remove vertical portions, reducing the interface area by preserving horizontal portions, thus optimizing chip space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interface regions are used to separate different types of devices, then device differentiation is achieved, but chip area occupancy increases
Solution Approach 1:
The patent transitions from planar interface regions to three-dimensional stacked layers. Multiple device types are vertically stacked above each other, separated by intermediate layers in the vertical dimension rather than requiring lateral interface regions. This dimensional change allows different device types to coexist in the same lateral footprint while maintaining clear separation through vertical stacking and intermediate layers.
Solution Approach 2:
The patent implements a nested structure where multiple device layers are stacked vertically, with each layer containing different device types. The layers are nested within the same lateral footprint, with intermediate layers positioned between different device types to provide separation. This nesting approach eliminates the need for lateral interface regions while maintaining device differentiation.
2Manufacturing precision
If stacked layers are formed with conformal layers, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent segments the stacked structure into multiple conformal layers deposited sequentially. Each layer is deposited with specific conformality requirements, and intermediate layers are inserted between different device types. This segmentation allows precise control of each layer's properties while maintaining overall manufacturing precision through standardized conformal deposition processes.
Data Source
AI summary
A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.