Vertically Stacked LDMOS-CMOS Package for Shorter Signal Paths
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Solution Overview
Problem
Conventional chip packaging technologies face challenges in signal transmission speed and layout area utilization, leading to inadequate electrical performance and limited space for additional functional elements in high-voltage power integrated circuits.
Innovation Solution
An electronic package design integrating LDMOS and CMOS chips into a chip module using conductive pillars and an encapsulation layer, with conductive bumps for electrical connection and a flush encapsulation surface, reducing space requirements and shortening electrical transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If LDMOS and CMOS chips are placed on different positions on the circuit board surface, then each chip can be independently packaged, but the signal transmission speed between chips becomes too slow and electrical performance requirements cannot be met
Solution Approach 1:
The patent merges LDMOS and CMOS chips into a single integrated chip module package, where both chip types are co-packaged with direct inter-chip connections. This eliminates the need for separate packaging while enabling high-speed signal transmission through short transmission lines within the same package, thus resolving the contradiction between ease of manufacture and signal transmission speed.
Solution Approach 2:
The patent transitions from a two-dimensional layout on the circuit board to a three-dimensional integrated package structure. By stacking chips vertically and using conductive pillars for inter-layer connections, the design achieves high-speed signal transmission while maintaining compact form factor, effectively moving from planar arrangement to spatial integration.
2Ease of manufacture
If LDMOS and CMOS chips are placed on different positions on the circuit board surface, then each chip can be independently packaged, but the layout area occupied becomes too large and more functional elements cannot be arranged
Solution Approach 1:
The patent combines multiple chip types (LDMOS and CMOS) into a single integrated package, dramatically reducing the total layout area required on the circuit board. This merging approach maintains the independence of each chip type while achieving compact integration, allowing additional functional elements to be arranged in the freed-up space.
Solution Approach 2:
The patent employs a nested package structure where different chip types are integrated within a single package housing. The chips are arranged in a compact configuration with support structures and transmission lines nested within the same package volume, achieving high integration density while maintaining individual chip functionality.
3Adaptability or versatility
If the functional element with antenna function is added outside the packaging body, then the antenna function can be provided, but the layout area of the circuit board needs to be enlarged
Solution Approach 1:
The patent integrates the antenna function directly into the chip module package by incorporating antenna elements within the packaging structure itself. This merging of communication function with the package structure eliminates the need for separate external antenna elements, maintaining versatility while minimizing layout area requirements.
Solution Approach 2:
The packaging structure is designed to serve multiple functions simultaneously: mechanical protection, electrical connection, signal transmission, and antenna radiation. By making the package structure multi-functional, the design achieves adaptability for wireless communication without requiring additional external components that would increase layout area.
Data Source
AI summary
An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.