Stacked Leaded Array for Capacitor Volumetric Efficiency
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Solution Overview
Problem
Existing electronic circuit designs face challenges in miniaturization and increasing functionality within a given volume, particularly in capacitors, where further miniaturization of individual components is limited and enhancing interconnectivity and packaging is required for improved volumetric efficiency.
Innovation Solution
A stacked leaded array of electronic components, including capacitors, is developed, allowing for vertical and horizontal stacking with minimal footprint, enabling the combination of components of different sizes and functionalities in a common package, with improved functionality per unit volume through the use of interconnects and insulators for efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If individual capacitor components are miniaturized to increase capacitance per unit volume, then volumetric efficiency is improved, but further miniaturization requires significant technical discovery and reaches practical limits
Solution Approach 1:
Multiple individual capacitor components are combined into a single stacked array assembly, where multiple capacitors are vertically and horizontally stacked together. This merging approach achieves further volumetric efficiency improvement without requiring additional miniaturization of individual capacitor components, thereby avoiding the technical difficulties associated with further miniaturization.
Solution Approach 2:
The patent transitions from two-dimensional planar arrangement of capacitors to three-dimensional stacked arrangement. By stacking capacitors vertically and horizontally in multiple layers, the system achieves increased capacitance per unit volume by utilizing the third dimension (height), thereby improving volumetric efficiency without reducing individual component size.
2Area of stationary object
If the surface area of the capacitor array is reduced to improve volumetric efficiency, then volume utilization is improved, but the height requirements must be maintained within maximum limits
Solution Approach 1:
The patent redistributes capacitor volume from horizontal spread to vertical stacking. By arranging capacitors in multiple stacked layers with optimized lead frame configurations, the design reduces the required surface footprint while maintaining acceptable height within maximum limits, thereby improving volumetric efficiency.
Solution Approach 2:
Multiple capacitor components are nested within a compact stacked array structure, where capacitors are arranged in concentric or layered configurations. This nesting approach maximizes the use of available vertical space while minimizing the horizontal footprint, achieving reduced surface area without excessive height increase.
3Volume of stationary object
If components are stacked vertically and horizontally to reduce footprint, then volumetric efficiency is improved, but complex interconnect structures are required to maintain electrical connectivity
Solution Approach 1:
The lead frame structure is designed to perform multiple functions simultaneously: it provides electrical connectivity between stacked capacitors, provides mechanical support for the stacked array, and enables compact packaging. This multi-functional design reduces the need for separate interconnect structures, thereby reducing overall device complexity despite the stacked configuration.
Solution Approach 2:
The patent merges the interconnect function with the lead frame structure itself, rather than using separate interconnect components. The lead frames are configured to directly connect capacitors in the stacked array, eliminating the need for additional interconnect layers or structures, thereby simplifying the overall device architecture despite the complex stacking arrangement.
Data Source
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AI summary
A stacked leaded array is provided wherein the stacked leaded array allows for increased packing density of electronic components (21). The stacked leaded array has a multiplicity of electronic components (21) in a stacked array. Each electronic component (21) comprises a first termination (20) and a second termination (22). A multiplicity of first leads (28,28') are provided wherein each first lead (28,28') is in electrical contact with at least one first termination (20). Second leads (26) are in electrical contact with second terminations (22).