Stacked Voltage-Domain Level Shifting With Moving Supply Rails

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Solution Overview

Problem

Conventional level conversion mechanisms in electronic interfaces and charge recycling fabrics are constrained by the gate-to-source voltage of pull-down and pull-up transistors, limiting the operational frequency range and efficiency of signal propagation between different voltage domains.

Innovation Solution

The use of PMOS and NMOS devices as pull-down and pull-up transistors, respectively, with dynamic gate voltages controlled by inverters, increases the effective gate-to-source voltage, enabling faster level conversion by utilizing a 'moving supply voltage' that adjusts during circuit operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional NMOS pull-down or PMOS pull-up transistors are used for level conversion, then the circuit structure is simple, but the level conversion speed is constrained by the gate-to-source voltage with respect to the magnitude of the lower supply voltage

Engineering Contradiction:
Improvelevel conversion speedVSAvoidcircuit structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements dynamic supply voltage switching where the supply voltage to the inverter is changed based on the input signal state. When the input signal is at the lower voltage level, the inverter receives the higher supply voltage to enable fast transition. This dynamic adjustment of supply voltage allows the circuit to achieve high-speed level conversion while maintaining a relatively simple structure by utilizing the inherent voltage levels already present in the system

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the supply voltage parameter dynamically based on operating conditions. By switching between higher and lower supply voltages depending on the input signal state, the circuit optimizes the gate-to-source voltage of the pull-down transistor, thereby achieving faster level conversion speed without requiring a completely different circuit architecture

Inventive Principle:
Principle #35Parameter changes

2Speed

If the gate-to-source voltage is increased to improve level conversion speed, then the operational frequency range increases, but the power consumption increases

Engineering Contradiction:
Improvelevel conversion speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic switching of the supply voltage to the inverter based on the input signal transitions. The supply voltage is increased only during the periods when level conversion is needed (when the input signal changes state), and reduced during stable periods. This periodic action allows the circuit to achieve high-speed conversion when required while minimizing power consumption during steady-state operation

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit dynamically adjusts the supply voltage to match the operational needs. Higher supply voltage is applied only during active transition periods to enable fast level conversion, while lower supply voltage is used during stable periods to reduce power consumption. This dynamic adaptation resolves the contradiction between speed and power by making the power consumption proportional to the actual conversion activity

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12047067B2Level-conversion circuits for signaling across voltage domains
Publication Date: 2024.07.23 NVIDIA CORP
  • US12047067B2 patent drawing
  • US12047067B2 patent drawing
  • US12047067B2 patent drawing

AI summary

Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.