Stacked Light Sensor Layout for On-Chip Neural Image Processing
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Solution Overview
Problem
Existing imaging apparatuses lack the capability to execute highly advanced image processing within a chip, necessitating more sophisticated processing for diversification and enhanced security of personal information.
Innovation Solution
A stacked light receiving sensor with a three-layer structure, comprising a pixel array section on the first layer, an analog circuit on one or more of the first to third layers, a logic circuit and processing section on the second and third layers, and a memory storing a neural network computing model, enabling advanced processing within the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a single-chip stacked structure is used to miniaturize the imaging apparatus, then the device size is reduced, but the capability to execute highly advanced processing within the chip is limited
Solution Approach 1:
The imaging apparatus is segmented into multiple functional layers: a first substrate containing pixel array sections for light reception, a second substrate containing logic circuits and processing sections, and a third substrate containing memory. This segmentation allows each layer to be optimized for its specific function while collectively enabling advanced processing capabilities within a compact stacked structure.
Solution Approach 2:
The patent transitions from a conventional two-dimensional planar arrangement to a three-dimensional stacked configuration by joining multiple substrates vertically. This dimensional change enables higher integration density and more complex processing functions within a reduced footprint, as circuits and memory can be arranged across multiple vertical layers rather than competing for horizontal space.
2Adaptability or versatility
If multiple circuits and memory are integrated on the same substrate, then processing capability is enhanced, but noise interference increases and image quality deteriorates
Solution Approach 1:
Noisy digital circuits (logic circuits and processing sections) are segmented and placed on a separate second substrate from the sensitive pixel array on the first substrate. This physical separation segments the noise sources from the signal sources, preventing digital switching noise from interfering with the delicate optical signals while still enabling integrated processing through the stacked configuration.
Solution Approach 2:
An electromagnetic shield is introduced as an intermediary layer between the pixel array section on the first substrate and the logic circuit on the second substrate. This shield acts as a mediator that blocks electromagnetic noise from the logic circuit from reaching the pixel array, thereby protecting image quality while allowing the noisy digital circuits to operate at full capacity on the adjacent substrate.
3Productivity
If advanced image processing is executed within the chip, then productivity and security are improved, but device complexity increases
Solution Approach 1:
The complex processing functions are segmented into modular components distributed across different substrates: pixel array sections on the first substrate, logic circuits and processing sections on the second substrate, and memory on the third substrate. This segmentation of complexity allows each substrate to be designed and manufactured with focused functionality, making the overall complex system more manageable and manufacturable.
Solution Approach 2:
Multiple functional components (pixel array, logic circuits, processing section, and memory) that would traditionally require separate chips are merged into a single stacked package. This merging of functions into one integrated stacked device enables high-speed processing and data transfer between components while maintaining a unified chip-scale form factor.
Data Source
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AI summary
More highly advanced processing is executed within a chip. A stacked light receiving sensor according to an embodiment includes: a first substrate (100/300) that forms a first layer; a second substrate (120/320) that is joined with the first substrate and that forms a second layer; a third substrate (140/340) that is joined with the second substrate and that forms a third layer; a pixel array section (101) that includes a plurality of unit pixels arranged two-dimensionally in a matrix; an analog circuit (201) that reads a pixel signal from the pixel array section; a logic circuit (202) that is connected to the analog circuit and that outputs the pixel signal; a memory (15) that stores therein a neural network computing model; a processing section (14) that executes processing based on the neural network computing model, on data based on the pixel signal; and an output section (16) that can output a processing result at least based on the neural network computing model to an outside. The pixel array section is disposed on the first layer. The analog circuit is disposed on any one or more of the first to third layers. The logic circuit, the processing section, and the memory are disposed on any one or more of the second and third layers.