Stacked Conductor Lines With Air Gaps for Lower Interconnect Capacitance
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Solution Overview
Problem
As spacing between conductor lines in integrated circuits decreases, capacitance increases, leading to performance penalties due to capacitive delay, and existing techniques struggle to effectively manage this issue without resorting to difficult high aspect ratio etching techniques.
Innovation Solution
The use of stacked conductor lines with air gaps in interlevel dielectric layers, integrated into double damascene metallization processes, allows for higher aspect ratio conductor lines with reduced resistance and capacitance, utilizing existing barrier layers and materials, and avoiding the need for extreme etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If spacing between conductor lines is decreased to increase routing density, then chip area utilization improves, but capacitance between adjacent lines increases causing performance degradation
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between adjacent conductor lines. This dielectric layer has lower permittivity than conventional dielectrics, thereby reducing the capacitance between closely-spaced conductor lines while allowing them to maintain small spacing for high routing density
Solution Approach 2:
The permittivity parameter of the dielectric material between conductor lines is changed to a lower value. This parameter change directly reduces the capacitance between adjacent lines, allowing tighter spacing without the performance penalty of capacitive delay
2Manufacturing precision
If conventional dielectric material is deposited by CVD to fill gaps between adjacent lines, then gap filling is achieved, but the opposing walls become coated with dielectric and bridge over leaving air gaps
Solution Approach 1:
The harmful dielectric coating on the opposing walls is selectively removed through etch-back or chemical-mechanical polishing. This extraction of excess dielectric material prevents bridging and maintains the intended air gap structure while preserving the gap-filling function in non-critical areas
Solution Approach 2:
The dielectric material is deposited in excess to ensure complete gap filling, then the excess material on the opposing walls is removed through planarization. This partial removal approach ensures gaps are filled where needed while eliminating problematic bridging regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces conductor line resistance, improves routing efficiency, and enhances electromigration and power droop performance, while minimizing the number of lines required, thus improving chip area utilization and reducing output driver sensitivity.
Implementation Method 1
As the dielectric material is deposited by chemical vapor deposition, the opposing walls of the adjacent lines become coated with dielectric
Data Source
AI summary
Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.