Stacked Logic Chip Package With Nested Substrate Bonding
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Solution Overview
Problem
There is a need for semiconductor packages with improved electrical properties and increased structural stability, while also simplifying the fabrication process and reducing costs.
Innovation Solution
The semiconductor package comprises a lower redistribution substrate with a logic structure, connection terminals, and connection structures, along with external connection terminals. It includes a first logic chip on a first redistribution substrate within an opening of a connection substrate, and a second logic chip on a dielectric pattern covered by a molding layer containing a resin material with fillers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a semiconductor chip is mounted on a PCB with bonding wires or bumps, then electrical connection is achieved, but the package size and complexity increase
Solution Approach 1:
The patent merges the connection substrate and logic chip into an integrated structure where the logic chip is directly mounted on the connection substrate within an opening, eliminating the need for separate bonding wire or bump structures. This integration reduces both package size and connection structure complexity while maintaining electrical connectivity.
Solution Approach 2:
The logic chip is nested within the opening of the connection substrate, creating a compact configuration where components are housed within each other. This nesting approach minimizes the overall package volume while keeping the connection structure simple and direct.
2Adaptability or versatility
If multiple logic chips are stacked vertically, then functionality is increased, but manufacturing precision requirements increase
Solution Approach 1:
The connection substrate is prepared in advance with pre-formed openings and connection structures before the logic chips are mounted. This preliminary preparation ensures that when chips are stacked vertically, they align with pre-defined connection points, reducing the precision requirements during the actual stacking process.
Solution Approach 2:
The connection substrate acts as an intermediary between multiple logic chips, providing a stable platform with pre-configured connection structures. This intermediary layer simplifies the stacking process by providing fixed reference points and connection interfaces, thereby reducing manufacturing precision requirements.
3Reliability
If a complex multi-layer structure is used, then electrical properties are improved, but fabrication complexity and cost increase
Solution Approach 1:
The connection substrate features localized connection structures and openings only where needed for specific electrical connections, rather than a complex multi-layer structure throughout. This local quality approach maintains necessary electrical properties while simplifying the overall fabrication process and reducing complexity.
Data Source
AI summary
A semiconductor package includes a lower redistribution substrate, a logic structure on the lower redistribution substrate, connection terminals between the lower redistribution substrate and the logic structure, connection structures on the lower redistribution substrate and surrounding the logic structure in plan view, and external connection terminals below the lower redistribution substrate. The logic structure includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having an opening in the connection substrate, a first logic chip on the first redistribution substrate and in the opening in the connection substrate, and a second logic chip on the connection substrate and the first logic chip. A first active surface of the first logic chip faces a second active surface of the second logic chip.