Stacked Logic and Memory Chip Substrate Integration
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Solution Overview
Problem
Current multi-chip modules face challenges in achieving low memory access times and high performance while minimizing cost, particularly with the increasing demand for quick memory access in cloud computing, machine learning, and artificial intelligence applications.
Innovation Solution
The solution involves a stacked logic chip and memory stack configuration where the memory stack is either placed on top of or beneath the logic chip, reducing parasitic capacitance and allowing for the use of either leading-edge or less expensive memory chips, thereby enhancing performance and reducing costs by minimizing motherboard surface area and power delivery complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If memory stack is placed close to logic chip to reduce access time, then memory access time is reduced, but parasitic capacitance increases
Solution Approach 1:
A semiconductor chip substrate acts as an intermediary between the logic chip and memory stack, providing controlled impedance traces that manage signal integrity while enabling close proximity stacking. The substrate mediates the electrical connection, allowing the memory stack to be positioned near the logic chip for reduced access time while the substrate's trace design controls parasitic capacitance effects.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture. By stacking memory chips vertically on the semiconductor substrate and positioning the logic chip in another layer, the design reduces the physical distance for signal transmission while distributing parasitic capacitance across multiple layers and connection points, thereby achieving both fast access and controlled parasitics.
2Loss of time
If leading-edge memory chips are used to achieve high performance, then memory access time is reduced, but cost increases
Solution Approach 1:
The memory system is segmented into a stack of multiple memory chips rather than using a single large high-performance chip. This allows the use of smaller, less expensive memory chips in the stack while achieving equivalent or better performance through parallel access paths and reduced individual chip parasitics, thereby reducing overall cost while maintaining fast access times.
3Area of stationary object
If memory stack and logic chip are stacked to reduce footprint, then area is reduced, but power delivery complexity increases
Solution Approach 1:
The semiconductor chip substrate serves multiple functions simultaneously: it provides mechanical support for stacking, establishes electrical connections through controlled impedance traces, manages power delivery to multiple chips, and controls signal integrity. This multi-functionality consolidates what would otherwise be separate complex subsystems into a single integrated platform, reducing overall system complexity despite the stacked architecture.
Data Source
AI summary
An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.