Stacked Long-Channel Transistor Layout to Prevent Nanosheet Collapse
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling beyond 5 nm due to increasing process complexities and costs, particularly in fabricating long channel devices within high-density stacked transistor structures, where nanosheets tend to collapse during fabrication.
Innovation Solution
The solution involves a stacked long channel transistor structure comprising multiple transistor arrays with continuous channel paths and interconnect structures, where horizontal and vertical strap interconnects form electrical connections between the arrays, enabling the fabrication of long channel devices in a dense configuration by aligning and connecting individual transistors to function as a single long channel device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional chip scaling is continued, then transistor density increases, but process complexities and costs escalate
Solution Approach 1:
The patent transitions from planar 2D transistor arrangements to three-dimensional stacked transistor structures. Multiple transistor arrays are stacked vertically with interconnect structures forming continuous channels through multiple layers, enabling higher density without proportionally increasing process complexity by utilizing the vertical dimension for integration.
2Quantity of substance
If stacked transistor structures are used, then transistor density increases, but nanosheets collapse during fabrication
Solution Approach 1:
The continuous channel is segmented into multiple discrete nanosheet portions, each forming part of the channel in different transistor arrays. These segmented nanosheets are spaced apart vertically, preventing collapse while maintaining electrical continuity through the stacked structure via interconnect elements.
Solution Approach 2:
Interconnect structures serve as intermediary elements between the nanosheet channels of different transistor arrays. These interconnects provide the necessary mechanical support and electrical connection, allowing the nanosheets to maintain their structural integrity while forming a continuous channel path through the stacked configuration.
3Reliability
If long channel devices are fabricated, then device performance improves, but fabrication difficulty increases at high density
Solution Approach 1:
The long channel is constructed by segmenting it into multiple shorter channel portions, each located in different transistor arrays within the stack. This segmentation allows standard fabrication processes to create each segment independently, while the overall structure achieves the cumulative long channel length needed for improved device performance.
Solution Approach 2:
The patent achieves long channel lengths by utilizing the vertical stacking dimension rather than extending channels laterally. Multiple channel segments are stacked vertically and connected via interconnect structures, creating an effective long channel path without requiring complex lateral fabrication processes.
Data Source
AI summary
A long channel transistor structure including a first transistor array adjacent to a second transistor array, a third transistor array adjacent to a fourth transistor array, where the third transistor array and the fourth transistor array are arranged above the first transistor array and the second transistor array, and a continuous channel path through channels of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.