Stacked MBCFET Gate Layout for Dense and Stable Contacts
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration and reducing capacitance and electrical instability as they are scaled down, requiring improved design for enhanced performance.
Innovation Solution
A semiconductor device design where an upper semiconductor element with a gate electrode is stacked on a lower semiconductor element, featuring overlapping gate electrodes and strategically positioned contacts to enhance integration and electrical stability, utilizing a Multi-Bridge Channel Field Effect Transistor (MBCFET) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase integration, then the degree of integration is improved, but electrical stability between contacts deteriorates
Solution Approach 1:
The patent transitions from planar 2D contact arrangement to 3D vertical stacking, where upper and lower gate electrodes are positioned at different vertical levels. This dimensional change allows contacts to be spaced apart in the vertical direction while maintaining high integration density, thereby improving electrical stability without sacrificing integration degree.
Solution Approach 2:
The patent implements a stacked structure where upper semiconductor elements are positioned above lower semiconductor elements, with upper gate electrodes overlapping lower gate electrodes in the vertical direction. This nesting arrangement maximizes space utilization and maintains high integration while providing vertical separation for electrical stability.
2Quantity of substance
If upper and lower gate electrodes are stacked to improve integration, then the degree of integration is improved, but contact spacing and electrical stability become challenging
Solution Approach 1:
The patent divides the semiconductor structure into distinct upper and lower sections with separate gate electrodes, source/drain regions, and contacts. This segmentation allows independent optimization of each section while maintaining overall integration, making the complex spacing arrangement more manageable through modular design.
Solution Approach 2:
By utilizing the vertical dimension for stacking upper and lower gate electrodes, the patent resolves contact spacing issues without increasing horizontal complexity. The vertical separation provides natural spacing while maintaining integration density.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a lower substrate; a lower active pattern which extends in a first direction on the lower substrate; a first lower gate electrode which extends in a second direction on the lower active pattern; an upper substrate on the first lower gate electrode; an upper active pattern which extends in the first direction on the upper substrate, wherein the upper active pattern is spaced apart from the lower active pattern in each of the second direction and a vertical direction; a first upper gate electrode which extends in the second horizontal direction on the upper active pattern, wherein the first upper gate electrode at least partially overlaps the first lower gate electrode in the vertical direction; and a first gate contact which is spaced apart from the first upper gate electrode in the second horizontal direction.