Stacked MCU Flash Architecture for Read-While-Write OTA Upgrades
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Solution Overview
Problem
Conventional MCU chips face inefficiencies due to the inability to perform simultaneous read, write, and erase operations on flash memory dies, which hampers operating efficiency and supports for over-the-air (OTA) upgrades.
Innovation Solution
The proposed MCU chip architecture includes two flash memory dies connected to the MCU die via separate bus interfaces, allowing for address mapping control to enable temporal sequences of access, thereby supporting read-while-write operations and efficient OTA upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single flash memory die is used with the MCU die, then the device complexity is reduced, but the operating efficiency deteriorates due to inability to perform simultaneous read, write and erase operations
Solution Approach 1:
The flash memory storage function is segmented into multiple independent flash memory dies (at least two), each capable of independent read, write, and erase operations. This segmentation allows parallel operations between different flash dies, resolving the contradiction by enabling simultaneous operations while maintaining relatively simple individual die structures.
Solution Approach 2:
Multiple flash memory dies are merged with the MCU die through separate bus interfaces within a single package, creating a unified system that supports parallel operations. The merging of multiple storage units with the processing unit enables the system to achieve high operating efficiency while keeping each component relatively simple.
2Device complexity
If a single flash memory die is used, then the device structure is simplified, but the OTA upgrade efficiency deteriorates due to poor support for simultaneous operations
Solution Approach 1:
The flash memory system is segmented into multiple independent dies, allowing OTA upgrade operations to be performed on one flash die while simultaneously reading or writing on another flash die. This segmentation enables parallel processing during upgrades, significantly reducing upgrade time while maintaining a relatively simple overall structure.
Solution Approach 2:
The system performs preliminary actions by preparing upgrade firmware in one flash die while simultaneously executing or validating firmware in another flash die. This preliminary preparation enables seamless transitions and reduces actual upgrade time, resolving the contradiction between simple structure and fast upgrades.
3Productivity
If address mapping control is implemented for multiple flash memory dies, then the operating efficiency is improved through parallel operations, but the device complexity increases
Solution Approach 1:
The MCU die acts as an intermediary that manages multiple flash memory dies through separate bus interfaces. The address mapping control logic is implemented within the MCU die, which mediates between the host system and multiple flash dies, enabling parallel operations while centralizing the complexity management in a single component rather than distributing it across multiple components.
Data Source
AI summary
The present invention provides an MCU chip composed of an MCU die and two or more flash memory dies stacked and packaged with the MCU die. In order to update firmware by means of an OTA upgrade, an OTA upgrade version of the firmware may be programmed into a second flash memory die, and an older version of the firmware may be stored in a first flash memory die. In this way, programming the OTA upgrade version of the firmware into the second flash memory die does not affect any operation in the first flash memory die, allowing RWW operations in the MCU chip. As a result, the influence of erase and program operations in the flash memory dies on operating efficiency of the firmware is greatly reduced, resulting in increases in operating performance, operating efficiency, support to OTA upgrades and upgrading efficiency of the MCU chip.