Stacked Memory Die Access Control for Mixed-Protocol Security
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Solution Overview
Problem
Existing technologies face challenges in managing secure access and efficient operation of multiple memory dies stacked in a common package, particularly when dies of different types and access protocols are mixed, leading to complexity and inefficiency.
Innovation Solution
A primary memory die controls access to secondary memory dies by managing their Chip Select (CS) inputs, allowing for different memory types and protocols, and operates in various access modes to manage secure access and data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies of different types and protocols are stacked in a common package, then storage capacity and functionality are improved, but access control complexity and security management deteriorate
Solution Approach 1:
The patent introduces a primary memory die that acts as an intermediary controller between the host device and secondary memory dies. The primary die receives commands from the host, determines the target die based on address ranges, and selectively activates appropriate CS lines to route commands to the correct secondary die. This intermediary approach allows multiple different memory types to coexist without requiring complex host-side control logic.
Solution Approach 2:
The patent segments the address space into different ranges, where each range is mapped to a specific secondary memory die. The primary memory die uses these segmented address ranges to determine which CS line to activate, thereby routing commands to the appropriate target die. This segmentation approach simplifies the control mechanism by creating clear boundaries between different memory die access regions.
2Reliability
If a primary memory die controls access to secondary memory dies by managing their Chip Select inputs, then access security and control are improved, but signal routing complexity deteriorates
Solution Approach 1:
The patent combines multiple CS control functions into a single primary memory die. Instead of having separate control circuits for each secondary die, the primary die consolidates the intelligence for determining target dies and controlling all CS lines from one location. This merging reduces overall system complexity while maintaining secure access control, as the primary die serves as a centralized security gatekeeper.
3Adaptability or versatility
If mixed memory technologies like NOR and NAND are supported in the same package, then versatility and functionality are improved, but protocol compatibility and access management deteriorate
Solution Approach 1:
The primary memory die serves as a protocol translator and mediator between the host device and secondary memory dies with different protocols. It receives commands from the host, identifies the target die type based on address ranges, and manages the appropriate protocol interactions with each secondary die. This allows NOR and NAND flash memory with different access protocols to coexist in the same package without requiring the host to understand multiple protocol variations.
Data Source
AI summary
An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.