Stacked Semiconductor Memory Device With Adhesive Insulating Layers
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing electric characteristics and increasing integration density while maintaining reliability, particularly in forming more circuits within a limited chip region with differing technical requirements between cell array and peripheral regions.
Innovation Solution
The solution involves a semiconductor memory device structure where different circuit regions are optimized on separate substrates, with contact plugs connecting the cell array region to core and peripheral circuit regions, allowing for optimized electric characteristics and improved reliability, and a method of fabricating these devices by stacking and bonding substrates with specific insulating layers to reduce interference and enhance design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more circuits are formed in a limited chip region to meet increasing demand for high integration, then integration density increases, but reliability deteriorates due to process interference between different circuit regions with differing technical requirements
Solution Approach 1:
The semiconductor device is divided into multiple separate substrates, with each substrate dedicated to specific circuit regions (e.g., cell array region on first substrate, peripheral circuit region on second substrate). This segmentation isolates different circuit regions that have differing technical requirements, preventing process interference while maintaining high integration density through vertical stacking of substrates.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Multiple substrates are stacked vertically and connected through adhesive insulating layers and contact plugs, enabling high integration density in the vertical dimension while maintaining independent optimization of each circuit region on separate substrates, thus resolving the reliability issue.
2Reliability
If different circuit regions are optimized independently, then electric characteristics are improved for each region, but device complexity increases due to multiple substrates and interconnection structures
Solution Approach 1:
The adhesive insulating layers serve multiple functions: they provide electrical insulation between substrates, mechanically bond the substrates together, and enable vertical stacking for high integration. The contact plugs simultaneously penetrate multiple layers (substrates and insulating layers) to establish electrical connections. This multi-functionality reduces the need for additional specialized components, managing complexity while enabling independent optimization of different circuit regions.
3Volume of moving object
If substrates are stacked and bonded with insulating layers, then form factor is reduced and integration density increases, but manufacturing complexity increases due to precise alignment and bonding requirements
Solution Approach 1:
Adhesive insulating layers are formed on substrate surfaces before the stacking and bonding processes. This preliminary action prepares the surfaces with appropriate adhesive properties and insulation characteristics, facilitating subsequent bonding operations. The pre-formed adhesive layers simplify the stacking process by ensuring proper alignment and adhesion, reducing manufacturing complexity despite the multi-step stacking procedure.
Data Source
AI summary
Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.