Semiconductor Accelerator With Memory Stacked Over Arithmetic Circuits
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Solution Overview
Problem
Semiconductor devices with accelerators face issues of high power consumption, heat generation, increased size, and frequent data transfers due to limited storage capacity and parasitic capacitance in wiring, especially when processing large amounts of data for AI applications.
Innovation Solution
Incorporating a semiconductor device with a CPU and an accelerator that includes memory circuits with OS transistors, allowing data retention during power gating, and stacking memory layers over arithmetic circuits to reduce power consumption and data transfer frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the accelerator has large storage capacity for retaining weight data, then data transfer frequency is reduced, but device size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture, placing memory circuits in layers above the arithmetic circuit. This vertical stacking increases storage capacity without expanding the device's footprint, thereby reducing data transfer frequency while maintaining compact size.
Solution Approach 2:
The patent implements a nested structure where memory circuits are integrated directly over the arithmetic circuit in a stacked configuration. This nesting allows the memory to be embedded within the vertical space above the computing units, maximizing storage capacity within the device volume.
2Speed
If high-speed data transmission is implemented, then data transfer frequency increases, but power consumption increases due to parasitic capacitance
Solution Approach 1:
The patent extracts the memory function from a separate chip and integrates it directly into the accelerator chip in a stacked configuration. This integration eliminates the need for high-speed external data transmission, reducing power consumption associated with parasitic capacitance while maintaining fast data access through direct vertical connections.
3Productivity
If AI processing with large calculations is performed, then computational performance improves, but heat generation increases
Solution Approach 1:
The patent distributes computational units and memory units across multiple vertical layers, enabling three-dimensional heat dissipation pathways. This vertical arrangement improves thermal management by allowing heat to dissipate in the vertical dimension, reducing hot spots and overall temperature while maintaining high computational performance.
4Speed
If memory circuits are integrated closer to arithmetic circuits, then data transfer speed improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the accelerator into distinct functional layers: an arithmetic circuit layer and memory circuit layers stacked above it. This segmentation allows each layer to be manufactured and optimized independently using standard semiconductor fabrication processes, then combined through layer-by-layer stacking, thereby managing manufacturing complexity while achieving fast data transfer.
Data Source
AI summary
To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.