Stacked Memory Cell Array Wiring for Chip Area Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in managing chip area expansion due to the need for increased integration and connectivity of memory cell arrays.
Innovation Solution
A semiconductor memory device design featuring a stacked configuration with separate electrical connections for select gate lines between memory cell arrays, while sharing word lines and bit lines, thereby optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory cell arrays are stacked and fully independently connected, then each array can be controlled separately improving reliability, but chip area increases due to redundant wiring
Solution Approach 1:
The patent applies universality by enabling word lines and bit lines to serve multiple memory cell arrays simultaneously. A single word line can be shared across multiple stacked arrays, and bit lines can connect to multiple arrays through via holes, allowing these wiring components to perform multiple functions and reducing the need for separate dedicated connections for each array.
Solution Approach 2:
The patent merges control resources by combining the word line and bit line infrastructure across multiple memory cell arrays. Instead of providing completely separate wiring for each array, the design merges the connection paths so that shared word lines and bit lines control multiple arrays, thereby reducing total wiring quantity and chip area while maintaining operational independence through selective activation.
2Measurement precision
If separate select gate lines are provided for each memory cell array, then array selection precision is improved, but device complexity increases due to additional wiring
Solution Approach 1:
The patent transitions from a two-dimensional planar wiring approach to a three-dimensional stacked architecture. Select gate lines are extended into the vertical dimension to access and control multiple stacked memory cell arrays. This dimensional change allows selective control of individual arrays within the stack without requiring separate select gate lines for each array in the traditional plane, thereby reducing wiring complexity while maintaining selection precision.
Solution Approach 2:
The patent segments the memory cell arrays into independently controllable units within the stacked structure. Each array can be selectively activated or deactivated through the extended select gate lines, allowing precise control of individual segments (arrays) while sharing common word lines and bit lines. This segmentation enables selective operation without requiring complete wiring independence for each array.
3Adaptability or versatility
If more wiring connections are added to connect multiple memory cell arrays, then connectivity and controllability are improved, but manufacturing precision requirements increase
Solution Approach 1:
By making word lines and bit lines universal across multiple arrays, the patent reduces the total number of unique wiring connections required. Instead of creating numerous array-specific connections that would demand high manufacturing precision, the design uses fewer multi-functional wiring paths, thereby lowering the cumulative precision requirements while maintaining full connectivity and controllability across all stacked arrays.
Data Source
AI summary
A semiconductor memory device includes first and second memory cell arrays. The first array includes a first semiconductor portion, extending in a first direction, on which a first memory cell and a first select transistor are formed, a first word line connected to the first cell, a first select gate line connected to the first transistor, and a first bit line connected to the first semiconductor portion. The second array includes a second semiconductor portion, extending along the first direction, on which a second memory cell and a second select transistor are formed, a second word line connected to the second cell, a second select gate line connected to the second transistor, and a second bit line connected to the second semiconductor portion. The first and second word lines are electrically connected, but the first and second select gate lines are not electrically connected.