Stacked Memory Cell Arrays With Contact Plugs for Lower Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There are limitations in increasing the number of memory holes and electrode layers in traditional memory devices due to restricted chip size, which hinders the enhancement of storage capacity.
Innovation Solution
A memory device design that stacks multiple memory cell arrays and connects them via contact plugs and connection pads, allowing for equivalent storage capacity to be achieved with fewer electrode layers, reducing electric resistance and maintaining cell current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrode layers and memory holes is increased to enlarge storage capacity, then storage capacity is improved, but device complexity and manufacturing difficulty increase due to restricted chip size
Solution Approach 1:
The memory device is divided into multiple memory cell arrays (first memory cell array, second memory cell array, etc.), each with a manageable number of electrode layers. This segmentation allows the total storage capacity to be distributed across multiple smaller units, reducing the complexity of manufacturing each individual array while achieving high overall capacity.
Solution Approach 2:
Multiple memory cell arrays are stacked in the vertical direction (first direction) to increase storage capacity without expanding the lateral chip area. This three-dimensional stacking approach enables capacity expansion by utilizing the vertical dimension, thereby avoiding the need to increase the number of electrode layers within a single planar array.
2Quantity of substance
If the number of electrode layers is increased to increase storage capacity, then storage capacity is improved, but electric resistance increases which affects cell current
Solution Approach 1:
The memory device segments the electrode layers into multiple memory cell arrays, where each array has a limited number of stacked electrode layers. This segmentation reduces the cumulative electric resistance within each array compared to a single array with many more layers, thereby maintaining better cell current characteristics while achieving high total capacity through parallel arrays.
Solution Approach 2:
By stacking multiple memory cell arrays vertically and connecting them via contact plugs, the design reduces the number of electrode layers needed within each array to achieve equivalent storage capacity. This reduces the electric resistance path length within each array, maintaining lower resistance and better current flow compared to a single tall stack.
3Area of stationary object
If the chip size is reduced to maintain device compactness, then device footprint is improved, but the number of memory holes and electrode layers that can be accommodated is limited
Solution Approach 1:
Multiple memory cell arrays are stacked in the vertical direction (first direction) above the substrate, enabling storage capacity expansion without increasing the lateral chip footprint. This three-dimensional configuration allows high capacity in a compact form factor by utilizing vertical space rather than lateral expansion.
Solution Approach 2:
The contact plugs serve multiple functions: they electrically connect bit lines between stacked memory cell arrays, provide mechanical support for the stacked structure, and enable signal transmission across different vertical levels. This multi-functionality allows compact integration without requiring additional dedicated components.
Data Source
AI summary
A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.