Stacked Semiconductor Memory Assembly With Attachment Film Vias
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Solution Overview
Problem
Current semiconductor memory devices face limitations in increasing integration density due to the high cost of miniaturization technologies and the need for higher functionality, speed, and miniaturization in electronic components, which restricts the development of three-dimensional memory devices.
Innovation Solution
A semiconductor memory device design featuring stacked semiconductor chips with a substrate attachment film that connects the chips, allowing for improved integration and reliability by using a mold structure with gate electrodes and channel structures, and contact vias for electrical connectivity, facilitating easier design and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor memory devices are used, then the structure is simple and manufacturing is easier, but the degree of integration is restricted due to area limitations
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory chips, utilizing the vertical dimension to increase integration density. Multiple memory chips are stacked in the third dimension (Z-axis) and connected through through-silicon vias (TSVs), enabling significantly higher storage capacity without increasing the footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple memory chips are stacked one on top of another, with each chip containing complete memory cell arrays, word lines, and bit lines. The chips are interconnected through vertical conductive paths, creating a compact nested architecture that maximizes space utilization.
2Quantity of substance
If three-dimensional stacked semiconductor chips are used, then the degree of integration increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the large-scale memory device into multiple independent but identical smaller memory chips, each functioning as a complete memory unit. This segmentation allows for modular manufacturing, testing, and assembly, reducing the complexity of producing a single large monolithic memory device while achieving high integration through stacking.
Solution Approach 2:
Each stacked memory chip is designed with universal functionality, containing complete memory cell arrays, word lines, bit lines, and control circuits that can operate independently. This multi-functionality allows any chip in the stack to serve multiple purposes, simplifying the overall system architecture and interconnection requirements.
3Ease of manufacture
If conventional substrate attachment methods are used, then the attachment process is simple, but the reliability and electrical connectivity between stacked chips are insufficient
Solution Approach 1:
The patent introduces an intermediary attachment layer between stacked memory chips that provides both mechanical bonding and electrical connectivity. This intermediate structure includes conductive materials and vias that facilitate signal transmission between chips while ensuring reliable physical attachment, solving the dual requirement of simple attachment process and high reliability.
Solution Approach 2:
The patent performs preliminary formation of contact vias and conductive structures within each memory chip before stacking. This preliminary action ensures that electrical connection paths are pre-established and aligned, enabling reliable inter-chip connectivity without requiring complex post-assembly alignment procedures, thus maintaining manufacturing simplicity while achieving high reliability.
Data Source
AI summary
A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.