Stacked Oxide Semiconductor Memory With Layer-Specific Back-Gate Bias

Solution Overview

Problem

In semiconductor devices with stacked layers of silicon and oxide transistors, variations in electrical characteristics due to heat generation lead to increased power consumption and reduced reliability, affecting memory density and performance.

Innovation Solution

Incorporating a temperature sensing circuit and voltage generation circuit to control back gate voltages in stacked oxide semiconductor transistors, with higher voltages applied to upper layers to mitigate temperature-induced variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a plurality of layers including OS transistors are stacked three-dimensionally to increase transistor density, then memory density is improved, but variations in electrical characteristics among layers increase due to temperature differences

Engineering Contradiction:

Improvetransistor densityVSAvoidelectrical characteristic uniformity

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by supplying different back gate voltages to different layers of OS transistors based on their local temperature conditions. Upper layers receive higher back gate voltages while lower layers receive lower voltages, compensating for temperature-induced threshold voltage variations in each specific location

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the back gate voltage parameter to compensate for temperature effects. By dynamically adjusting the back gate voltage level according to layer position and temperature, the threshold voltage variations are corrected, maintaining uniform electrical characteristics across all stacked layers

Inventive Principle:

Principle #35Parameter changes

2Reliability

If back gate voltage is increased to compensate for threshold voltage variations in upper layers, then electrical characteristic uniformity is improved, but power consumption increases

Engineering Contradiction:

Improveelectrical characteristic uniformityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by supplying different back gate voltages to different layers of OS transistors based on their local temperature conditions. Upper layers receive higher back gate voltages while lower layers receive lower voltages, compensating for temperature-induced threshold voltage variations in each specific location

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the back gate voltage parameter to compensate for temperature effects. By dynamically adjusting the back gate voltage level according to layer position and temperature, the threshold voltage variations are corrected, maintaining uniform electrical characteristics across all stacked layers

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces variations in electrical characteristics, enhances memory density, and lowers power consumption while maintaining high-speed operation and reliability.

Implementation Method 1

The temperature sensing circuit has a function of controlling the back gate voltage in accordance with a sensed temperature

Methodology Applied

Scientific EffectTemperature sensing:

Implementation Method 2

The voltage generation circuit has a function of generating a back gate voltage supplied to the back gate. The voltage generation circuit has a function of supplying the back gate voltage different between the plurality of second element layers

Methodology Applied

Scientific EffectVoltage generation:

Data Source

PatentUS20250322866A1Semiconductor device

Publication Date: 2025.10.16 SEMICON ENERGY LAB CO LTD

AI summary

A semiconductor device with a novel structure is provided. A first element layer and a plurality of second element layers each including a temperature sensing circuit, a voltage generation circuit, and memory cells are provided. The plurality of second element layers are stacked over the first element layer. The memory cell includes a transistor in which a semiconductor layer including a channel formation region includes an oxide semiconductor. The transistor includes a back gate. The voltage generation circuit provided in each layer has a function of generating a back gate voltage supplied to the back gate of the transistor included in the memory cell provided in the same layer. The temperature sensing circuit has a function of controlling the back gate voltage in accordance with a sensed temperature. In the second element layers, the back gate voltage supplied to the transistor included in the second element layer provided in an upper layer is higher than the back gate voltage supplied to the transistor included in the second element layer provided in a lower layer.