Stacked Memory Interface Die With Backside Power Delivery
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Solution Overview
Problem
Providing stable and reliable power delivery to semiconductor assemblies with complex power delivery networks is challenging due to the large power consumption and routing complexity with signal layers, especially in multi-stack memory devices.
Innovation Solution
Implementing a backside power delivery network (BSPDN) on the interface die and separating power traces from signal traces, combined with power conditioning devices embedded in the substrate, to improve power delivery efficiency and reduce routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power delivery network is implemented on the same side as signal layers, then routing is simplified, but power delivery stability deteriorates due to interference and congestion
Solution Approach 1:
The interface die is divided into two functional sides: one side handles signal processing while the other side is dedicated to power delivery. This segmentation separates power traces from signal traces, eliminating electromagnetic interference and routing congestion while ensuring stable power delivery to the stacked memory devices.
Solution Approach 2:
The power delivery network is moved from the traditional planar routing approach to a dedicated backside layer of the interface die. This dimensional separation allows power traces to be routed independently from signal traces, improving both power delivery stability and reducing routing complexity on the front side.
2Ease of manufacture
If power conditioning devices are located far from memory devices, then manufacturing is simplified, but power delivery efficiency deteriorates
Solution Approach 1:
Power conditioning devices are pre-positioned on the backside of the interface die in close proximity to where the stacked memory devices will be mounted. This preliminary positioning ensures that power delivery paths are minimized before final assembly, improving power delivery efficiency without complicating the manufacturing process.
3Quantity of substance
If multiple memory device stacks are connected to interface die, then device density increases, but power delivery reliability deteriorates due to increased power consumption
Solution Approach 1:
The interface die is segmented into multiple independent power delivery regions on its backside, each region capable of serving a separate memory device stack. This segmentation allows each stack to receive dedicated, stable power delivery while maintaining high device density through the use of multiple stacks connected to the same interface die.
Data Source
AI summary
A device may include an interface die, a first memory device stack connected to a first side of the interface die, a second memory device stack connected to the first side of the interface die, and a power distribution network located on a second side of the interface die. A system may include a substrate comprising at least one distribution layer, a compute die connected to the at least one distribution layer, and a memory stack device connected to the at least one distribution layer, wherein the memory stack device may include an interface die connected to the at least one distribution layer, a first stack of memory devices connected to the interface die, and a second stack of memory devices connected to the interface die. The substrate may include an attachment location, and the compute die may be located within the attachment location.