Interleaved Stacked Memory Dies for Balanced I/O Wire Bonds
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in achieving balanced electrical signal strength and integrity across multiple I/O channels, which can lead to variations in voltage drop and resistance, affecting overall performance and reliability.
Innovation Solution
The memory device employs a stacked configuration of first and second memories interleaved between each other, with first and second wire bonds electrically coupling these memories to separate I/O channels of a memory controller. This configuration ensures that the total combined length of the first wire bonds is within a specific tolerance (e.g., 30% or 20%) of the total combined length of the second wire bonds, balancing voltage drop and resistance across both I/O channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are mounted on a substrate with conventional wiring, then memory capacity and density are increased, but variations in voltage drop and resistance occur across different I/O channels, degrading signal integrity
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional stacked configuration, arranging memory devices vertically along the Z-axis. This dimensional change allows multiple memory devices to be mounted while maintaining controlled wire bond lengths through alternating stack positions, thereby preserving signal integrity across I/O channels while increasing memory capacity
Solution Approach 2:
The patent segments the wire bond connections by alternating their attachment positions between first and second stacks. First wire bonds connect to first stack positions and second wire bonds connect to second stack positions, creating segmented connection paths that balance the total length of wire bonds for each I/O channel, thus reducing resistance and voltage drop variations
2Ease of manufacture
If wire bond lengths are not balanced across I/O channels, then manufacturing complexity is reduced, but voltage drop and resistance variations increase, affecting performance
Solution Approach 1:
The patent changes the geometric parameter of wire bond routing by utilizing alternating stack positions (first and second stacks) to control total wire bond length. This parameter change ensures that wire bonds from different I/O channels traverse similar distances, balancing electrical characteristics while maintaining manufacturing feasibility through standardized alternating patterns
3Area of stationary object
If memory devices are arranged in a stack configuration, then footprint area is reduced, but achieving balanced wire bond lengths across I/O channels becomes more difficult
Solution Approach 1:
The patent employs asymmetric positioning of memory devices within the stack, creating distinct first and second stacks with alternating connections to different I/O channels. This asymmetric arrangement, where first wire bonds connect to first stack positions and second wire bonds connect to second stack positions, enables balanced wire bond lengths while maintaining compact three-dimensional footprint
Data Source
AI summary
Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.