Stacked Memory Channel Layout for Higher Bandwidth Density
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Solution Overview
Problem
Existing data processing systems are limited by hardware component architecture, which restricts communication bandwidth and device density, leading to reduced performance in computer-implemented services.
Innovation Solution
Implementing a data processing system with stacked memory devices and multiple memory channels, utilizing high-density fingers and signal buffer logic to manage independent communication channels, and employing multi-die memory devices to increase bandwidth and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory architecture is used, then device density is limited, but system volume remains large
Solution Approach 1:
The patent transitions from planar memory device arrangement to three-dimensional stacked architecture, where multiple memory devices are vertically stacked and interconnected through interposers. This dimensional change enables significantly higher device density within the same footprint while reducing the overall system volume required.
Solution Approach 2:
The patent implements nested interconnection structures where interposers are embedded within the stacked memory device architecture. Each interposer contains multiple interconnect layers that are nested within the vertical stack, allowing multiple communication channels to be integrated within the compact three-dimensional structure.
2Productivity
If single memory channel is used, then communication bandwidth is limited, but device complexity increases with multiple channels
Solution Approach 1:
The patent divides the memory interconnection into multiple independent memory channels, each handled by separate buffer logic units. This segmentation allows parallel data transmission across multiple channels, increasing overall communication bandwidth while distributing the control complexity across multiple independent modules rather than one complex centralized controller.
Solution Approach 2:
The patent introduces buffer logic as an intermediary component between the processor and stacked memory devices. The buffer logic manages data transmission across multiple memory channels, absorbing the complexity of multi-channel coordination and presenting a simplified interface to both the processor and memory devices, thereby increasing bandwidth without proportionally increasing overall system complexity.
Data Source
AI summary
A data processing system is disclosed. The data processing system may include a processor, memory module, and circuit board. The circuit board may include a first socket for the processor. The circuit board may include a second socket for the memory module. The circuit board may also include a first physical memory channel interconnecting a first portion of the first socket and a first portion of the second socket. The circuit board may additionally include a second physical memory channel interconnecting a second portion of the first socket and a second portion of the second socket.