Stacked Memory Scalable Bandwidth Interface
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Solution Overview
Problem
Conventional stacked memory devices with through silicon vias (TSV) face challenges in scaling bandwidth as more memory chips are added, leading to increased manufacturing costs that outweigh the benefits, especially in systems with wide memory buses.
Innovation Solution
The memory device employs a scalable bandwidth interface by grouping data bus connections into four-bit nibbles and rotating connections within each group, allowing each memory device to have an exclusive data bus, which enables the system to scale up data rate without increasing fetch size, and includes a programmable I/O driver to selectively use data bus contacts based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If through silicon vias (TSV) are used to connect stacked memory devices, then lead lengths are reduced and signal distortion is minimized, but manufacturing cost increases
Solution Approach 1:
The data bus connections are segmented into groups of four-bit nibbles, with each group rotated to connect to different contact pads on the next die. This segmentation allows the system to maintain a manageable contact pad footprint while achieving high bandwidth, resolving the contradiction between signal quality and manufacturing complexity.
Solution Approach 2:
The patent introduces a rotational dimension to the traditional linear data bus connection scheme. By rotating connections within each nibble group, the system achieves bandwidth scaling without proportionally increasing the contact pad footprint, effectively adding a dimensional transformation to the inter-die connection architecture.
2Productivity
If more memory chips are stacked to increase bandwidth, then memory capacity increases, but manufacturing cost increases proportionally
Solution Approach 1:
The contact pads and TSV connections are designed to serve multiple functions across different die configurations. The same contact pad structure can support different numbers of stacked dies (e.g., 2D versus 3D stacking), making the manufacturing process more universal and reducing the incremental cost of adding more memory chips.
Solution Approach 2:
The data bus connection scheme is designed to be dynamic and adaptable, allowing the system to configure different bandwidth modes by selectively activating different nibble groups. This dynamic reconfigurability enables the system to scale bandwidth with memory capacity without requiring proportional increases in manufacturing complexity.
3Productivity
If data bus width is increased to scale bandwidth, then memory bandwidth increases, but device complexity increases
Solution Approach 1:
The data bus is segmented into multiple independent four-bit nibble groups, each of which can be rotated and connected to different contact pads. This segmentation allows the system to achieve high bandwidth through parallel nibble transmission while keeping each individual connection path simple and manageable, thus reducing overall device complexity.
Solution Approach 2:
Instead of simply increasing data bus width in a linear fashion, the patent introduces a rotational dimension to the connection scheme. By rotating connections within each nibble group, the system achieves bandwidth scaling without proportionally increasing the contact pad footprint or connection complexity, effectively using dimensional transformation to manage complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases memory bandwidth as more devices are added without the need for increased data bus width, reducing manufacturing costs and maintaining low signal distortion, thus enhancing the return on investment for stacked memory architectures.
Implementation Method 1
holes are created through each die from one side to the other, and the holes are metallized. When the dice are aligned and mechanically bonded, a die-to-die electrical pathway (or bus) is created from each signal on the top die all the way through all of the dice to a contact pad on the bottom surface of the bottom die.
Implementation Method 2
The substrate also includes a metallization layer formed on the second surface. Each of the external data contact pads may be arranged in vertical alignment with a respective contact pad on the second surface.
Data Source
AI summary
A memory device having a scalable bandwidth I/O data bus includes a semiconductor die having a substrate with a first and a second surface. The substrate includes contact pads arranged in rows across the first surface and across the second surface. The contact pads on one surface may be physically arranged in vertical alignment with a corresponding contact pad on the other surface and may be electrically coupled to the corresponding contact pad using a via. The substrate also includes a metallization layer formed on the second surface. The metallization layer includes external data contact pads each arranged in vertical alignment with a respective contact pad on the second surface. Each row of contact pads may be grouped, and the external contact pads within a group are electrically coupled to an adjacent contact pad on the second surface by effectively logically shifting them to the right one contact pad.