Stacked Semiconductor Memory Bandwidth Through Time-Division Multiplexing

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Solution Overview

Problem

Conventional stacked semiconductor memory devices face challenges in increasing bandwidth while minimizing the number of through electrodes, which leads to increased chip area and reduced yield due to defects in manufacturing.

Innovation Solution

The solution involves activating multiple memory arrays in response to an access request and sequentially connecting them to a common data through electrode, allowing for high-speed data transfer without the need for multiple through electrodes, thereby increasing bandwidth while reducing the number of electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple through electrodes are used to increase bandwidth, then data transfer speed is improved, but chip area increases and manufacturing yield decreases

Engineering Contradiction:
ImprovebandwidthVSAvoidchip area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic time-division multiplexing where a single through electrode sequentially connects to multiple memory arrays at different time slots. The connection switching is controlled dynamically based on access requests, allowing one physical electrode to serve multiple logical channels, thereby increasing bandwidth without proportionally increasing chip area

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent transitions from spatial parallelism (multiple simultaneous through electrodes) to temporal parallelism (single through electrode switching in time). By adding the time dimension to data transfer, the system achieves multi-array access through a single electrode, effectively increasing bandwidth without the area cost of multiple physical electrodes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple through electrodes are used to increase bandwidth, then data transfer speed is improved, but manufacturing reliability decreases due to more defects

Engineering Contradiction:
ImprovebandwidthVSAvoidmanufacturing yield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges multiple data transfer functions into a single through electrode by implementing time-division multiplexing. Instead of having separate electrodes for each memory array, the system combines access to multiple arrays through one shared electrode with temporal separation, reducing the total number of electrodes and associated defect points

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single through electrode is designed to be universal, serving multiple memory arrays through controlled switching. This multi-functional electrode replaces what would traditionally require multiple specialized electrodes, one per memory array, thereby reducing manufacturing complexity and improving yield

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If one through electrode is shared by multiple memory arrays, then chip area is reduced, but data transfer bandwidth is limited

Engineering Contradiction:
Improvechip areaVSAvoidbandwidth
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent implements periodic time-division multiplexing where the single through electrode cycles through connections with different memory arrays in regular time slots. This periodic switching allows multiple arrays to share the electrode resource systematically, achieving high effective bandwidth through efficient time utilization rather than requiring simultaneous physical connections

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8076766B2Stacked semiconductor memory device
Publication Date: 2011.12.13 MICRON TECHNOLOGY INC
  • US8076766B2 patent drawing
  • US8076766B2 patent drawing
  • US8076766B2 patent drawing

AI summary

A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.