3D Stacked Memory Chip Architecture for Lower Bit Cost
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Solution Overview
Problem
Current semiconductor storage devices face challenges in reducing manufacturing costs per storage capacity due to high wafer costs associated with high-performance transistors and complex chip configurations.
Innovation Solution
The solution involves stacking memory chips and a circuit chip, where the circuit chip includes a data latch and peripheral circuits, and the memory chips are connected via micro-bumps and via wirings, reducing the number of I/O signal lines and transmission frequency, thereby lowering the performance requirements and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-performance transistors are used to maintain signal transmission quality, then transmission reliability is improved, but wafer cost increases
Solution Approach 1:
The patent transitions from planar chip configuration to three-dimensional stacking architecture. Memory chips are stacked vertically on the circuit chip, enabling signal transmission through vertical interconnects (via wirings) rather than horizontal trace lines. This dimensional change reduces the number of I/O signal lines required and allows lower-performance transistors to suffice for each connection point, thereby reducing wafer cost while maintaining transmission reliability through the stacked architecture.
Solution Approach 2:
The patent divides the storage device into separate functional modules: memory chips containing memory cell arrays and a circuit chip containing control circuits and data latches. These segmented chips are stacked and interconnected, allowing each chip to be optimized independently. The circuit chip handles control functions with fewer high-performance transistors, while memory chips use simpler transistor designs, collectively reducing overall wafer cost while maintaining system reliability.
2Quantity of substance
If complex chip configurations are used to increase storage capacity, then storage capacity is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs three-dimensional stacking of multiple memory chips vertically on a single circuit chip. This vertical arrangement enables significantly increased storage capacity without proportionally increasing the footprint area or manufacturing complexity. Each stacked memory chip can be manufactured using standard processes, and the vertical integration multiplies capacity while keeping the base circuit chip design relatively simple, thereby improving capacity without linearly increasing manufacturing cost.
Solution Approach 2:
The circuit chip serves multiple functions: it contains control circuits for managing memory operations, data latches for temporary data storage, and I/O interface circuits for external communication. This multi-functional integration on a single chip reduces the need for separate dedicated chips, simplifying the overall manufacturing process while achieving high storage capacity through the stacked configuration.
3Speed
If the number of I/O signal lines is increased to improve data transmission speed, then transmission speed is improved, but chip complexity increases
Solution Approach 1:
The patent uses vertical stacking to create short inter-chip communication paths through via wirings, enabling fast data transmission between memory chips and the circuit chip. The three-dimensional arrangement reduces the physical distance signals must travel compared to planar configurations, achieving high transmission speed without requiring an excessive number of I/O signal lines. The stacked architecture inherently reduces complexity by consolidating connections in the vertical dimension.
Data Source
AI summary
A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.