Stacked Memory Bit-Line Bonding for High-Density Semiconductor Integration
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Solution Overview
Problem
The increasing demand for high-capacity data processing in semiconductor devices while minimizing their volume poses a challenge in achieving higher degrees of integration and reliability, particularly in conventional planar transistor structures.
Innovation Solution
A semiconductor device with a vertical transistor structure is proposed, comprising two substrate structures with stacked and spaced gate electrodes, channels, bit lines, and bonding pads. These structures are bonded together through the bonding pads, allowing for electrical connection between the bit lines and enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If vertical transistor structure with stacked gate electrodes is adopted, then degree of integration increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the transistor structure into multiple discrete stacked segments including separate gate electrodes, channels, and insulation layers. Each segment can be formed and positioned independently, allowing for modular manufacturing and easier alignment control compared to forming the entire vertical structure in a single complex process step.
Solution Approach 2:
The patent employs preliminary formation of insulation layers and sacrificial structures before depositing and patterning the gate electrodes and channels. These preliminary structures serve as templates and alignment guides that simplify subsequent stacking operations and ensure precise positioning of each layer relative to the others.
2Reliability
If substrate structures are bonded together through bonding pads, then reliability improves, but manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple functions into the bonding pads, which simultaneously serve as electrical connection terminals, mechanical bonding interfaces, and alignment reference features. This merging of functions reduces the need for separate alignment marks and simplifies the bonding process while maintaining reliable electrical connections between stacked substrate structures.
Data Source
AI summary
A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively. The first substrate structure and the second substrate structure are connected to each other by bonding the first bonding pads to the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines, without the first substrate or second substrate disposed vertically between the first bit lines and the second bit lines.