Stacked Memory String Bit-Line Layout With Offset Connection Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in achieving high-capacity data storage and efficient integration of memory cells, particularly in three-dimensionally arranged configurations, where existing solutions struggle to optimize the connection and control of memory strings and bit lines for enhanced performance.
Innovation Solution
The proposed memory device incorporates a design with vertically arranged memory strings and a peripheral circuit region that includes bit lines, bonding pads, and connection vias, where the bit lines and bonding pads are strategically positioned and offset to facilitate efficient electrical connections and improved integration, allowing for effective control of memory strings across multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory strings are arranged vertically in three-dimensional configuration, then data storage capacity is increased, but connection complexity and integration difficulty worsen
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking of memory strings. Multiple memory strings are stacked vertically across multiple levels, with bit lines extending horizontally to connect to bonding pads. This dimensional change increases storage capacity while the systematic layout manages connection complexity.
Solution Approach 2:
The memory device is divided into multiple levels with distinct functional regions. Each level contains memory strings, bit lines, and bonding pads arranged in a segmented manner. This segmentation allows independent optimization of each layer's connections and reduces overall integration difficulty.
2Reliability
If bit lines and bonding pads are positioned to facilitate efficient electrical connections, then operating characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The bit lines and bonding pads are positioned asymmetrically relative to each other, with bit lines extending from memory strings to bonding pads at offset positions. This asymmetric arrangement optimizes electrical connection paths and reduces interference, improving operating characteristics while establishing clear manufacturing alignment targets.
3Productivity
If multiple memory strings are connected through bonding pads and connection vias, then integration is improved, but connection path length increases
Solution Approach 1:
Connection vias serve as intermediary elements between bit lines at different levels and bonding pads. These vias provide direct vertical connection paths through the substrate, reducing the overall connection path length compared to surface-level routing alone, while enabling efficient integration of multiple memory strings.
Data Source
AI summary
A memory device is disclosed. The memory device includes a first cell region including first memory strings, a second cell region attached to the first cell region and including second memory strings, and a peripheral circuit region attached to the first cell region and including a peripheral circuit configured to control the first and second memory strings, the first cell region including a low-level bit line electrically connected to the first memory strings, a low-level bonding pad provided between the peripheral circuit region and the first cell region, a low-level connection via connected to the low-level bonding pad, a high-level bonding pad provided between the first and second cell regions, the second cell region including a high-level bit line electrically connected to the second memory strings, and a high-level connection via connected to the high-level bonding pad and being laterally offset from the low-level connection via.