3D Stacked Memory Bitline Selection to Reduce Sense Amplifier Load
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Solution Overview
Problem
The high density of memory cells in three-dimensional stacked volatile memory devices increases the load on bitline sense amplifiers due to narrowing spacing between bitlines and the increasing number of bitlines handled by a single sense amplifier.
Innovation Solution
A memory device is designed with a bitline selection circuit that selectively connects a portion of local bitlines to a global bitline based on an address received from a memory controller during read or write operations, reducing the load on bitline sense amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three dimensions to increase capacity, then storage capacity is improved, but the load on bitline sense amplifiers increases due to narrowing spacing and increasing number of bitlines
Solution Approach 1:
The bitline structure is segmented into local bitlines and global bitlines. Local bitlines are connected to memory cells, while global bitlines are connected to sense amplifiers. Intermediate bitlines serve as connectors between local and global bitlines. This segmentation allows the sense amplifier to interface with multiple local bitlines through a single global bitline, reducing the direct load on the sense amplifier while maintaining the ability to access numerous memory cells in the stacked array.
Solution Approach 2:
Intermediate bitlines act as mediators between local bitlines and global bitlines. They provide a buffering layer that distributes the signal load from multiple local bitlines to a single global bitline, thereby reducing the effective load on the sense amplifier. The intermediate bitlines enable signal aggregation and distribution without requiring the sense amplifier to directly handle all local bitlines.
2Quantity of substance
If the number of bitlines handled by a single sense amplifier is increased to support high density, then storage capacity is improved, but the complexity of the bitline structure increases
Solution Approach 1:
The bitline structure is divided into three functional layers: local bitlines (connected to memory cells), intermediate bitlines (grouping local bitlines), and global bitlines (connected to sense amplifiers). This multi-level segmentation organizes the complex interconnections in a hierarchical manner, making the signal routing and load distribution more manageable while supporting high-density storage.
Solution Approach 2:
Multiple local bitlines are merged and combined through intermediate bitlines to feed into a single global bitline. This merging process consolidates the signal paths, reducing the number of direct connections the sense amplifier must handle while maintaining access to multiple memory cell columns. The intermediate bitlines serve as merging points that aggregate signals from multiple sources.
Data Source
AI summary
An example memory device includes a bitline sense amplifier, a global bitline connected with the bitline sense amplifier, intermediate bitlines respectively connected with bonding pads electrically connecting a peripheral circuit structure and a cell array structure, local bitlines connected with each of the intermediate bitlines, memory cells connected with each of the local bitlines, and a bitline selection circuit selectively connecting a portion of the intermediate bitlines with the global bitline based on an address received from a memory controller during a read or write operation.