Stacked Memory Chip Bonding Shield for Bit-Line Interference

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Solution Overview

Problem

Existing semiconductor devices face challenges in increasing integration density while maintaining bonding reliability between semiconductor chips due to interference between bit lines and signal lines, and the need for additional shielding members can compromise this reliability.

Innovation Solution

A semiconductor device with a shielding member featuring a link pattern and island patterns in bonding metal layers of separate chips, configured in a grid or stripe shape, to minimize interference and maintain bonding reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If additional shielding members are added to block interference between bit lines and signal lines, then interference shielding is improved, but bonding reliability deteriorates

Engineering Contradiction:

Improveinterference between bit lines and signal linesVSAvoidbonding reliability

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The shielding member is merged with the bonding metal layer, forming a unified structure that performs both bonding and shielding functions simultaneously. The link pattern and island patterns are integrated into the bonding metal layer of the first substrate, eliminating the need for separate shielding structures that would compromise bonding reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bonding metal layer is given multiple functions: it serves as both the bonding interface for connecting substrates and as the shielding member to block interference between bit lines and signal lines. This multi-functional design resolves the contradiction by making the same structure serve dual purposes without adding extra components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If integration density is increased using POC structures, then degree of integration is improved, but interference between bit lines and signal lines worsens

Engineering Contradiction:

Improvedegree of integrationVSAvoidinterference between bit lines and signal lines

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The shielding function is merged into the bonding metal layer used in POC structures, allowing high integration density to be achieved while simultaneously blocking interference between bit lines and signal lines through the integrated shielding patterns.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12456694B2Semiconductor device having stacked memory cell array, peripheral circuit and shielding member

Publication Date: 2025.10.28 SK HYNIX INC

AI summary

A semiconductor device includes a first semiconductor chip including a memory cell array and a plurality of bit lines; a second semiconductor chip including a peripheral circuit, and bonded to the first semiconductor chip; and a shielding member including a link pattern that is configured in a bonding metal layer of any one of the first semiconductor chip and the second semiconductor chip, and has a grid shape or stripe shapes, and a plurality of island patterns that are configured in a bonding metal layer of the other one of the first semiconductor chip and the second semiconductor chip, and bonded to the link pattern.